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arch-arm: add size check for AdvSIMD copy

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imm5_pos and size are the output of findLsbSet. When imm5 is zero,
imm5_pos and size are 64 which will cause assert fail in the following
bits calls. We detect this case and return an Unknown instruction.

Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49827
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Yu-hsin Wang
2021-09-01 17:29:33 +08:00
parent c4852b35dd
commit a670993522
1 changed files with 12 additions and 0 deletions
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12
src/arch/arm/isa/formats/neon64.isa
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@@ -1205,6 +1205,9 @@ namespace Aarch64
if (!q || (imm4 & mask(imm5_pos)))
return new Unknown64(machInst);
if (imm5_pos > 3)
return new Unknown64(machInst);
index1 = bits(imm5, 4, imm5_pos + 1); // dst
index2 = bits(imm4, 3, imm5_pos); // src
@@ -1224,6 +1227,9 @@ namespace Aarch64
switch (imm4) {
case 0x0:
if (imm5_pos > 3)
return new Unknown64(machInst);
index1 = bits(imm5, 4, imm5_pos + 1);
switch (imm5_pos) {
case 0:
@@ -1289,6 +1295,9 @@ namespace Aarch64
return new Unknown64(machInst);
}
case 0x5:
if (imm5_pos > 3)
return new Unknown64(machInst);
index1 = bits(imm5, 4, imm5_pos + 1);
switch (imm5_pos) {
case 0:
@@ -2431,6 +2440,9 @@ namespace Aarch64
IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = findLsbSet(imm5);
if (size > 3)
return new Unknown64(machInst);
uint8_t index = bits(imm5, 4, size + 1);
return decodeNeonUTwoShiftUReg<DupElemScX>(