From a670993522aa76137e951f96d7ad3004f089790a Mon Sep 17 00:00:00 2001 From: Yu-hsin Wang Date: Wed, 1 Sep 2021 17:29:33 +0800 Subject: [PATCH] arch-arm: add size check for AdvSIMD copy imm5_pos and size are the output of findLsbSet. When imm5 is zero, imm5_pos and size are 64 which will cause assert fail in the following bits calls. We detect this case and return an Unknown instruction. Change-Id: I4ed2513267fff5b5bdb81723617ff74fb9f82482 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49827 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/isa/formats/neon64.isa | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa index 1948a34dc3..660d118efd 100644 --- a/src/arch/arm/isa/formats/neon64.isa +++ b/src/arch/arm/isa/formats/neon64.isa @@ -1205,6 +1205,9 @@ namespace Aarch64 if (!q || (imm4 & mask(imm5_pos))) return new Unknown64(machInst); + if (imm5_pos > 3) + return new Unknown64(machInst); + index1 = bits(imm5, 4, imm5_pos + 1); // dst index2 = bits(imm4, 3, imm5_pos); // src @@ -1224,6 +1227,9 @@ namespace Aarch64 switch (imm4) { case 0x0: + if (imm5_pos > 3) + return new Unknown64(machInst); + index1 = bits(imm5, 4, imm5_pos + 1); switch (imm5_pos) { case 0: @@ -1289,6 +1295,9 @@ namespace Aarch64 return new Unknown64(machInst); } case 0x5: + if (imm5_pos > 3) + return new Unknown64(machInst); + index1 = bits(imm5, 4, imm5_pos + 1); switch (imm5_pos) { case 0: @@ -2431,6 +2440,9 @@ namespace Aarch64 IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5); uint8_t size = findLsbSet(imm5); + if (size > 3) + return new Unknown64(machInst); + uint8_t index = bits(imm5, 4, size + 1); return decodeNeonUTwoShiftUReg(