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arch-arm: Remove Jazelle state support

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Jazelle state has been officially removed in Armv8.
Every AArch32 implementation must still support the
"Trivial Jazelle implementation", which means that while
the instruction set has been removed, it is still possible
for privileged software to access some Jazelle registers
like JIDR,JMCR, and JOSCR which are just treated as RAZ

Change-Id: Ie403c4f004968eb4cb45fa51067178a550726c87
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-06-05 09:44:22 +01:00
parent 3455d9e68d
commit a33f3d3967
14 changed files with 20 additions and 100 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/fastmodel/CortexA76/thread_context.cc
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@@ -228,7 +228,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({
// ArmISA::MISCREG_SCTLR_RST?
{ ArmISA::MISCREG_SEV_MAILBOX, "SEV_STATE" },
// AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
// AArch32 CP14 registers (debug/trace/ThumbEE control)
// ArmISA::MISCREG_DBGDIDR?
// ArmISA::MISCREG_DBGDSCRint?
// ArmISA::MISCREG_DBGDCCINT?

2
src/arch/arm/fastmodel/CortexR52/thread_context.cc
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@@ -188,7 +188,7 @@ Iris::ThreadContext::IdxNameMap CortexR52TC::miscRegIdxNameMap({
// ArmISA::MISCREG_SCTLR_RST?
// ArmISA::MISCREG_SEV_MAILBOX?
// AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
// AArch32 CP14 registers (debug/trace/ThumbEE control)
// ArmISA::MISCREG_DBGDIDR?
// ArmISA::MISCREG_DBGDSCRint?
// ArmISA::MISCREG_DBGDCCINT?

2
src/arch/arm/fastmodel/iris/thread_context.cc
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@@ -581,8 +581,6 @@ ThreadContext::pcState() const
pc.thumb(cpsr.t);
pc.nextThumb(pc.thumb());
pc.jazelle(cpsr.j);
pc.nextJazelle(cpsr.j);
pc.aarch64(!cpsr.width);
pc.nextAArch64(!cpsr.width);
pc.illegalExec(false);

4
src/arch/arm/faults.cc
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@@ -565,7 +565,6 @@ ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst)
cpsr.i = 1;
}
cpsr.it1 = cpsr.it2 = 0;
cpsr.j = 0;
cpsr.pan = span ? 1 : saved_cpsr.pan;
tc->setMiscReg(MISCREG_CPSR, cpsr);
@@ -622,8 +621,6 @@ ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst)
PCState pc(new_pc);
pc.thumb(cpsr.t);
pc.nextThumb(pc.thumb());
pc.jazelle(cpsr.j);
pc.nextJazelle(pc.jazelle());
pc.aarch64(!cpsr.width);
pc.nextAArch64(!cpsr.width);
pc.illegalExec(false);
@@ -666,7 +663,6 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
// Force some bitfields to 0
spsr.q = 0;
spsr.it1 = 0;
spsr.j = 0;
spsr.ge = 0;
spsr.it2 = 0;
spsr.t = 0;

2
src/arch/arm/isa.cc
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@@ -407,7 +407,6 @@ ISA::readMiscReg(RegIndex idx)
if (idx == MISCREG_CPSR) {
cpsr = miscRegs[idx];
auto pc = tc->pcState().as<PCState>();
cpsr.j = pc.jazelle() ? 1 : 0;
cpsr.t = pc.thumb() ? 1 : 0;
return cpsr;
}
@@ -678,7 +677,6 @@ ISA::setMiscReg(RegIndex idx, RegVal val)
miscRegs[idx], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
PCState pc = tc->pcState().as<PCState>();
pc.nextThumb(cpsr.t);
pc.nextJazelle(cpsr.j);
pc.illegalExec(cpsr.il == 1);
selfDebug->setDebugMask(cpsr.d == 1);

4
src/arch/arm/isa/formats/branch.isa
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@@ -212,10 +212,6 @@ def format Thumb32BranchesAndMiscCtrl() {{
{
const uint32_t op = bits(machInst, 7, 4);
switch (op) {
case 0x0:
return new Leavex(machInst);
case 0x1:
return new Enterx(machInst);
case 0x2:
return new Clrex(machInst);
case 0x4:

1
src/arch/arm/isa/insts/data.isa
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@@ -268,7 +268,6 @@ let {{
CondCodesGE = new_cpsr.ge;
NextThumb = (new_cpsr).t;
NextJazelle = (new_cpsr).j;
NextItState = (((new_cpsr).it2 << 2) & 0xFC)
| ((new_cpsr).it1 & 0x3);
SevMailbox = 1;

1
src/arch/arm/isa/insts/macromem.isa
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@@ -668,7 +668,6 @@ let {{
0xF, true, sctlr.nmfi, xc->tcBase());
Cpsr = ~CondCodesMask & new_cpsr;
NextThumb = new_cpsr.t;
NextJazelle = new_cpsr.j;
NextItState = ((((CPSR)URb).it2 << 2) & 0xFC)
| (((CPSR)URb).it1 & 0x3);
CondCodesNZ = new_cpsr.nz;

27
src/arch/arm/isa/insts/misc.isa
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@@ -173,9 +173,8 @@ let {{
CondCodesGE = new_cpsr.ge;
NextThumb = (new_cpsr).t;
NextJazelle = (new_cpsr).j;
NextItState = (((new_cpsr).it2 << 2) & 0xFC)
| ((new_cpsr).it1 & 0x3);
NextItState = (((new_cpsr).it2 << 2) & 0xFC)
| ((new_cpsr).it1 & 0x3);
NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR;
'''
@@ -1083,28 +1082,6 @@ let {{
exec_output += PredOpExecute.subst(mcrr15Iop)
enterxCode = '''
NextThumb = true;
NextJazelle = true;
'''
enterxIop = ArmInstObjParams("enterx", "Enterx", "PredOp",
{ "code": enterxCode,
"predicate_test": predicateTest }, [])
header_output += BasicDeclare.subst(enterxIop)
decoder_output += BasicConstructor.subst(enterxIop)
exec_output += PredOpExecute.subst(enterxIop)
leavexCode = '''
NextThumb = true;
NextJazelle = false;
'''
leavexIop = ArmInstObjParams("leavex", "Leavex", "PredOp",
{ "code": leavexCode,
"predicate_test": predicateTest }, [])
header_output += BasicDeclare.subst(leavexIop)
decoder_output += BasicConstructor.subst(leavexIop)
exec_output += PredOpExecute.subst(leavexIop)
setendCode = '''
CPSR cpsr = Cpsr;
cpsr.e = imm;

1
src/arch/arm/isa/operands.isa
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@@ -526,7 +526,6 @@ def operands {{
'IWNPC': PCStateReg('instIWNPC', srtPC),
'Thumb': PCStateReg('thumb', srtPC),
'NextThumb': PCStateReg('nextThumb', srtMode),
'NextJazelle': PCStateReg('nextJazelle', srtMode),
'NextItState': PCStateReg('nextItstate', srtMode),
'Itstate': PCStateReg('itstate', srtMode),
'NextAArch64': PCStateReg('nextAArch64', srtMode),

64
src/arch/arm/pcstate.hh
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@@ -75,7 +75,6 @@ class PCState : public GenericISA::UPCState<4>
enum FlagBits
{
ThumbBit = (1 << 0),
JazelleBit = (1 << 1),
AArch64Bit = (1 << 2)
};
@@ -202,36 +201,6 @@ class PCState : public GenericISA::UPCState<4>
}
bool
jazelle() const
{
return flags & JazelleBit;
}
void
jazelle(bool val)
{
if (val)
flags |= JazelleBit;
else
flags &= ~JazelleBit;
}
bool
nextJazelle() const
{
return nextFlags & JazelleBit;
}
void
nextJazelle(bool val)
{
if (val)
nextFlags |= JazelleBit;
else
nextFlags &= ~JazelleBit;
}
bool
aarch64() const
{
@@ -354,29 +323,18 @@ class PCState : public GenericISA::UPCState<4>
void
instIWNPC(Addr val)
{
bool thumbEE = (thumb() && jazelle());
Addr newPC = val;
if (thumbEE) {
if (bits(newPC, 0)) {
newPC = newPC & ~mask(1);
} // else we have a bad interworking address; do not call
// panic() since the instruction could be executed
// speculatively
if (bits(val, 0)) {
nextThumb(true);
val = val & ~mask(1);
} else if (!bits(val, 1)) {
nextThumb(false);
} else {
if (bits(newPC, 0)) {
nextThumb(true);
newPC = newPC & ~mask(1);
} else if (!bits(newPC, 1)) {
nextThumb(false);
} else {
// This state is UNPREDICTABLE in the ARM architecture
// The easy thing to do is just mask off the bit and
// stay in the current mode, so we'll do that.
newPC &= ~mask(2);
}
// This state is UNPREDICTABLE in the ARM architecture
// The easy thing to do is just mask off the bit and
// stay in the current mode, so we'll do that.
val &= ~mask(2);
}
npc(newPC);
npc(val);
}
// Perform an interworking branch in ARM mode, a regular branch
@@ -384,7 +342,7 @@ class PCState : public GenericISA::UPCState<4>
void
instAIWNPC(Addr val)
{
if (!thumb() && !jazelle())
if (!thumb())
instIWNPC(val);
else
instNPC(val);

2
src/arch/arm/regs/misc.hh
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@@ -96,7 +96,7 @@ namespace ArmISA
MISCREG_SEV_MAILBOX,
MISCREG_TLBINEEDSYNC,
// AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
// AArch32 CP14 registers (debug/trace/ThumbEE control)
MISCREG_DBGDIDR,
MISCREG_DBGDSCRint,
MISCREG_DBGDCCINT,

2
src/arch/arm/regs/misc_types.hh
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@@ -54,7 +54,7 @@ namespace ArmISA
Bitfield<28> v;
Bitfield<27> q;
Bitfield<26, 25> it1;
Bitfield<24> j;
Bitfield<24> dit; // AArch64
Bitfield<23> uao; // AArch64
Bitfield<22> pan;
Bitfield<21> ss; // AArch64

6
src/arch/arm/tracers/tarmac_base.cc
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@@ -107,12 +107,12 @@ TarmacBaseRecord::pcToISetState(const PCStateBase &pc)
if (apc.aarch64())
isetstate = TarmacBaseRecord::ISET_A64;
else if (!apc.thumb() && !apc.jazelle())
else if (!apc.thumb())
isetstate = TarmacBaseRecord::ISET_ARM;
else if (apc.thumb() && !apc.jazelle())
else if (apc.thumb())
isetstate = TarmacBaseRecord::ISET_THUMB;
else
// No Jazelle state in TARMAC
// Unsupported state in TARMAC
isetstate = TarmacBaseRecord::ISET_UNSUPPORTED;
return isetstate;