From a33f3d3967ef4f215986792986d6dd8c09392c9a Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Mon, 5 Jun 2023 09:44:22 +0100 Subject: [PATCH] arch-arm: Remove Jazelle state support Jazelle state has been officially removed in Armv8. Every AArch32 implementation must still support the "Trivial Jazelle implementation", which means that while the instruction set has been removed, it is still possible for privileged software to access some Jazelle registers like JIDR,JMCR, and JOSCR which are just treated as RAZ Change-Id: Ie403c4f004968eb4cb45fa51067178a550726c87 Signed-off-by: Giacomo Travaglini --- .../arm/fastmodel/CortexA76/thread_context.cc | 2 +- .../arm/fastmodel/CortexR52/thread_context.cc | 2 +- src/arch/arm/fastmodel/iris/thread_context.cc | 2 - src/arch/arm/faults.cc | 4 -- src/arch/arm/isa.cc | 2 - src/arch/arm/isa/formats/branch.isa | 4 -- src/arch/arm/isa/insts/data.isa | 1 - src/arch/arm/isa/insts/macromem.isa | 1 - src/arch/arm/isa/insts/misc.isa | 27 +------- src/arch/arm/isa/operands.isa | 1 - src/arch/arm/pcstate.hh | 64 ++++--------------- src/arch/arm/regs/misc.hh | 2 +- src/arch/arm/regs/misc_types.hh | 2 +- src/arch/arm/tracers/tarmac_base.cc | 6 +- 14 files changed, 20 insertions(+), 100 deletions(-) diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc index c6704852fc..26e7193803 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc @@ -228,7 +228,7 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::miscRegIdxNameMap({ // ArmISA::MISCREG_SCTLR_RST? { ArmISA::MISCREG_SEV_MAILBOX, "SEV_STATE" }, - // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) + // AArch32 CP14 registers (debug/trace/ThumbEE control) // ArmISA::MISCREG_DBGDIDR? // ArmISA::MISCREG_DBGDSCRint? // ArmISA::MISCREG_DBGDCCINT? diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc b/src/arch/arm/fastmodel/CortexR52/thread_context.cc index a20f8e0a89..45fa6e924f 100644 --- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc +++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc @@ -188,7 +188,7 @@ Iris::ThreadContext::IdxNameMap CortexR52TC::miscRegIdxNameMap({ // ArmISA::MISCREG_SCTLR_RST? // ArmISA::MISCREG_SEV_MAILBOX? - // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) + // AArch32 CP14 registers (debug/trace/ThumbEE control) // ArmISA::MISCREG_DBGDIDR? // ArmISA::MISCREG_DBGDSCRint? // ArmISA::MISCREG_DBGDCCINT? diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc index 462995a19a..0919251a9b 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.cc +++ b/src/arch/arm/fastmodel/iris/thread_context.cc @@ -581,8 +581,6 @@ ThreadContext::pcState() const pc.thumb(cpsr.t); pc.nextThumb(pc.thumb()); - pc.jazelle(cpsr.j); - pc.nextJazelle(cpsr.j); pc.aarch64(!cpsr.width); pc.nextAArch64(!cpsr.width); pc.illegalExec(false); diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc index 379e761f98..4b906f226f 100644 --- a/src/arch/arm/faults.cc +++ b/src/arch/arm/faults.cc @@ -565,7 +565,6 @@ ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst) cpsr.i = 1; } cpsr.it1 = cpsr.it2 = 0; - cpsr.j = 0; cpsr.pan = span ? 1 : saved_cpsr.pan; tc->setMiscReg(MISCREG_CPSR, cpsr); @@ -622,8 +621,6 @@ ArmFault::invoke32(ThreadContext *tc, const StaticInstPtr &inst) PCState pc(new_pc); pc.thumb(cpsr.t); pc.nextThumb(pc.thumb()); - pc.jazelle(cpsr.j); - pc.nextJazelle(pc.jazelle()); pc.aarch64(!cpsr.width); pc.nextAArch64(!cpsr.width); pc.illegalExec(false); @@ -666,7 +663,6 @@ ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) // Force some bitfields to 0 spsr.q = 0; spsr.it1 = 0; - spsr.j = 0; spsr.ge = 0; spsr.it2 = 0; spsr.t = 0; diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index a395d1a35f..f961a2d2c4 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -407,7 +407,6 @@ ISA::readMiscReg(RegIndex idx) if (idx == MISCREG_CPSR) { cpsr = miscRegs[idx]; auto pc = tc->pcState().as(); - cpsr.j = pc.jazelle() ? 1 : 0; cpsr.t = pc.thumb() ? 1 : 0; return cpsr; } @@ -678,7 +677,6 @@ ISA::setMiscReg(RegIndex idx, RegVal val) miscRegs[idx], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); PCState pc = tc->pcState().as(); pc.nextThumb(cpsr.t); - pc.nextJazelle(cpsr.j); pc.illegalExec(cpsr.il == 1); selfDebug->setDebugMask(cpsr.d == 1); diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa index ff6bfda54e..8213ab9ff8 100644 --- a/src/arch/arm/isa/formats/branch.isa +++ b/src/arch/arm/isa/formats/branch.isa @@ -212,10 +212,6 @@ def format Thumb32BranchesAndMiscCtrl() {{ { const uint32_t op = bits(machInst, 7, 4); switch (op) { - case 0x0: - return new Leavex(machInst); - case 0x1: - return new Enterx(machInst); case 0x2: return new Clrex(machInst); case 0x4: diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa index 31fc172883..cec761905e 100644 --- a/src/arch/arm/isa/insts/data.isa +++ b/src/arch/arm/isa/insts/data.isa @@ -268,7 +268,6 @@ let {{ CondCodesGE = new_cpsr.ge; NextThumb = (new_cpsr).t; - NextJazelle = (new_cpsr).j; NextItState = (((new_cpsr).it2 << 2) & 0xFC) | ((new_cpsr).it1 & 0x3); SevMailbox = 1; diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa index edd7228cf8..5e11c3ba95 100644 --- a/src/arch/arm/isa/insts/macromem.isa +++ b/src/arch/arm/isa/insts/macromem.isa @@ -668,7 +668,6 @@ let {{ 0xF, true, sctlr.nmfi, xc->tcBase()); Cpsr = ~CondCodesMask & new_cpsr; NextThumb = new_cpsr.t; - NextJazelle = new_cpsr.j; NextItState = ((((CPSR)URb).it2 << 2) & 0xFC) | (((CPSR)URb).it1 & 0x3); CondCodesNZ = new_cpsr.nz; diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa index 86e9e8943c..9ee753e385 100644 --- a/src/arch/arm/isa/insts/misc.isa +++ b/src/arch/arm/isa/insts/misc.isa @@ -173,9 +173,8 @@ let {{ CondCodesGE = new_cpsr.ge; NextThumb = (new_cpsr).t; - NextJazelle = (new_cpsr).j; - NextItState = (((new_cpsr).it2 << 2) & 0xFC) - | ((new_cpsr).it1 & 0x3); + NextItState = (((new_cpsr).it2 << 2) & 0xFC) + | ((new_cpsr).it1 & 0x3); NPC = (old_cpsr.mode == MODE_HYP) ? ElrHyp : LR; ''' @@ -1083,28 +1082,6 @@ let {{ exec_output += PredOpExecute.subst(mcrr15Iop) - enterxCode = ''' - NextThumb = true; - NextJazelle = true; - ''' - enterxIop = ArmInstObjParams("enterx", "Enterx", "PredOp", - { "code": enterxCode, - "predicate_test": predicateTest }, []) - header_output += BasicDeclare.subst(enterxIop) - decoder_output += BasicConstructor.subst(enterxIop) - exec_output += PredOpExecute.subst(enterxIop) - - leavexCode = ''' - NextThumb = true; - NextJazelle = false; - ''' - leavexIop = ArmInstObjParams("leavex", "Leavex", "PredOp", - { "code": leavexCode, - "predicate_test": predicateTest }, []) - header_output += BasicDeclare.subst(leavexIop) - decoder_output += BasicConstructor.subst(leavexIop) - exec_output += PredOpExecute.subst(leavexIop) - setendCode = ''' CPSR cpsr = Cpsr; cpsr.e = imm; diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa index 5bba00f138..5e6506d0e8 100644 --- a/src/arch/arm/isa/operands.isa +++ b/src/arch/arm/isa/operands.isa @@ -526,7 +526,6 @@ def operands {{ 'IWNPC': PCStateReg('instIWNPC', srtPC), 'Thumb': PCStateReg('thumb', srtPC), 'NextThumb': PCStateReg('nextThumb', srtMode), - 'NextJazelle': PCStateReg('nextJazelle', srtMode), 'NextItState': PCStateReg('nextItstate', srtMode), 'Itstate': PCStateReg('itstate', srtMode), 'NextAArch64': PCStateReg('nextAArch64', srtMode), diff --git a/src/arch/arm/pcstate.hh b/src/arch/arm/pcstate.hh index a2f0463fab..98e3202eb3 100644 --- a/src/arch/arm/pcstate.hh +++ b/src/arch/arm/pcstate.hh @@ -75,7 +75,6 @@ class PCState : public GenericISA::UPCState<4> enum FlagBits { ThumbBit = (1 << 0), - JazelleBit = (1 << 1), AArch64Bit = (1 << 2) }; @@ -202,36 +201,6 @@ class PCState : public GenericISA::UPCState<4> } - bool - jazelle() const - { - return flags & JazelleBit; - } - - void - jazelle(bool val) - { - if (val) - flags |= JazelleBit; - else - flags &= ~JazelleBit; - } - - bool - nextJazelle() const - { - return nextFlags & JazelleBit; - } - - void - nextJazelle(bool val) - { - if (val) - nextFlags |= JazelleBit; - else - nextFlags &= ~JazelleBit; - } - bool aarch64() const { @@ -354,29 +323,18 @@ class PCState : public GenericISA::UPCState<4> void instIWNPC(Addr val) { - bool thumbEE = (thumb() && jazelle()); - - Addr newPC = val; - if (thumbEE) { - if (bits(newPC, 0)) { - newPC = newPC & ~mask(1); - } // else we have a bad interworking address; do not call - // panic() since the instruction could be executed - // speculatively + if (bits(val, 0)) { + nextThumb(true); + val = val & ~mask(1); + } else if (!bits(val, 1)) { + nextThumb(false); } else { - if (bits(newPC, 0)) { - nextThumb(true); - newPC = newPC & ~mask(1); - } else if (!bits(newPC, 1)) { - nextThumb(false); - } else { - // This state is UNPREDICTABLE in the ARM architecture - // The easy thing to do is just mask off the bit and - // stay in the current mode, so we'll do that. - newPC &= ~mask(2); - } + // This state is UNPREDICTABLE in the ARM architecture + // The easy thing to do is just mask off the bit and + // stay in the current mode, so we'll do that. + val &= ~mask(2); } - npc(newPC); + npc(val); } // Perform an interworking branch in ARM mode, a regular branch @@ -384,7 +342,7 @@ class PCState : public GenericISA::UPCState<4> void instAIWNPC(Addr val) { - if (!thumb() && !jazelle()) + if (!thumb()) instIWNPC(val); else instNPC(val); diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 6a4933c5d6..6f5e9ead6c 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -96,7 +96,7 @@ namespace ArmISA MISCREG_SEV_MAILBOX, MISCREG_TLBINEEDSYNC, - // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control) + // AArch32 CP14 registers (debug/trace/ThumbEE control) MISCREG_DBGDIDR, MISCREG_DBGDSCRint, MISCREG_DBGDCCINT, diff --git a/src/arch/arm/regs/misc_types.hh b/src/arch/arm/regs/misc_types.hh index abbe2afa98..00d0cc49fa 100644 --- a/src/arch/arm/regs/misc_types.hh +++ b/src/arch/arm/regs/misc_types.hh @@ -54,7 +54,7 @@ namespace ArmISA Bitfield<28> v; Bitfield<27> q; Bitfield<26, 25> it1; - Bitfield<24> j; + Bitfield<24> dit; // AArch64 Bitfield<23> uao; // AArch64 Bitfield<22> pan; Bitfield<21> ss; // AArch64 diff --git a/src/arch/arm/tracers/tarmac_base.cc b/src/arch/arm/tracers/tarmac_base.cc index 99ed3bb0f1..25524d24b6 100644 --- a/src/arch/arm/tracers/tarmac_base.cc +++ b/src/arch/arm/tracers/tarmac_base.cc @@ -107,12 +107,12 @@ TarmacBaseRecord::pcToISetState(const PCStateBase &pc) if (apc.aarch64()) isetstate = TarmacBaseRecord::ISET_A64; - else if (!apc.thumb() && !apc.jazelle()) + else if (!apc.thumb()) isetstate = TarmacBaseRecord::ISET_ARM; - else if (apc.thumb() && !apc.jazelle()) + else if (apc.thumb()) isetstate = TarmacBaseRecord::ISET_THUMB; else - // No Jazelle state in TARMAC + // Unsupported state in TARMAC isetstate = TarmacBaseRecord::ISET_UNSUPPORTED; return isetstate;