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arch-arm: Use new fault callbacks in canRead/WriteAArch64SysReg

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This should be equivalent of checking the lookUpMiscReg[reg].info
bitset. The functions have been renamed to
checkFaultRead/WriteAArch64SysReg as they now return a fault and
not a boolean

Change-Id: I2d7465c368428a7d55eb48b32396315e23bcf0f9
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61677
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-07-07 17:36:51 +01:00
parent 79cbb0a668
commit 9bd4520b13
3 changed files with 21 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

17
src/arch/arm/isa/insts/data64.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2011-2013, 2016-2021 Arm Limited
// Copyright (c) 2011-2013, 2016-2022 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -312,9 +312,9 @@ let {{
msrMrs64EnabledCheckCode = '''
// Check for read/write access right
if (!can%sAArch64SysReg(flat_idx, Hcr64, Scr64, cpsr, xc->tcBase())) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
if (fault = checkFault%sAArch64SysReg(flat_idx, Hcr64, Scr64, cpsr,
xc->tcBase(), *this); fault != NoFault) {
return fault;
}
fault = this->trap(xc->tcBase(), flat_idx, el);
@@ -553,12 +553,9 @@ let {{
mnemonic);
}
if (!canWriteAArch64SysReg(misc_index, Hcr64,
Scr64, Cpsr, xc->tcBase())) {
return std::make_shared<UndefinedInstruction>(
machInst, 0, EC_TRAPPED_MSR_MRS_64,
mnemonic);
if (fault = checkFaultWriteAArch64SysReg(misc_index, Hcr64,
Scr64, Cpsr, xc->tcBase(), *this); fault != NoFault) {
return fault;
}
'''

71
src/arch/arm/regs/misc.cc
View File

@@ -723,77 +723,26 @@ unflattenMiscReg(int reg)
return unflattenResultMiscReg[reg];
}
bool
canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc)
Fault
checkFaultReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc, const MiscRegOp64 &inst)
{
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
return inst.undefined();
bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
const auto& miscreg_info = lookUpMiscReg[reg].info;
switch (currEL(cpsr)) {
case EL0:
return secure ? miscreg_info[MISCREG_USR_S_RD] :
miscreg_info[MISCREG_USR_NS_RD];
case EL1:
return secure ? miscreg_info[MISCREG_PRI_S_RD] :
miscreg_info[MISCREG_PRI_NS_RD];
case EL2:
if (el2_host) {
return secure ? miscreg_info[MISCREG_HYP_E2H_S_RD] :
miscreg_info[MISCREG_HYP_E2H_NS_RD];
} else {
return secure ? miscreg_info[MISCREG_HYP_S_RD] :
miscreg_info[MISCREG_HYP_NS_RD];
}
case EL3:
return el2_host ? miscreg_info[MISCREG_MON_E2H_RD] :
secure ? miscreg_info[MISCREG_MON_NS0_RD] :
miscreg_info[MISCREG_MON_NS1_RD];
default:
panic("Invalid exception level");
}
return lookUpMiscReg[reg].checkFault(tc, inst, currEL(cpsr));
}
bool
canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc)
Fault
checkFaultWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc, const MiscRegOp64 &inst)
{
// Check for SP_EL0 access while SPSEL == 0
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
ExceptionLevel el = currEL(cpsr);
return inst.undefined();
bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
const auto& miscreg_info = lookUpMiscReg[reg].info;
switch (el) {
case EL0:
return secure ? miscreg_info[MISCREG_USR_S_WR] :
miscreg_info[MISCREG_USR_NS_WR];
case EL1:
return secure ? miscreg_info[MISCREG_PRI_S_WR] :
miscreg_info[MISCREG_PRI_NS_WR];
case EL2:
if (el2_host) {
return secure ? miscreg_info[MISCREG_HYP_E2H_S_WR] :
miscreg_info[MISCREG_HYP_E2H_NS_WR];
} else {
return secure ? miscreg_info[MISCREG_HYP_S_WR] :
miscreg_info[MISCREG_HYP_NS_WR];
}
case EL3:
return el2_host ? miscreg_info[MISCREG_MON_E2H_WR] :
secure ? miscreg_info[MISCREG_MON_NS0_WR] :
miscreg_info[MISCREG_MON_NS1_WR];
default:
panic("Invalid exception level");
}
return lookUpMiscReg[reg].checkFault(tc, inst, currEL(cpsr));
}
std::vector<struct MiscRegLUTEntry> lookUpMiscReg(NUM_MISCREGS);

8
src/arch/arm/regs/misc.hh
View File

@@ -2879,12 +2879,12 @@ namespace ArmISA
bool AArch32isUndefinedGenericTimer(MiscRegIndex reg, ThreadContext *tc);
// Checks read access permissions to AArch64 system registers
bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc);
Fault checkFaultReadAArch64SysReg(MiscRegIndex reg, HCR hcr,
SCR scr, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst);
// Checks write access permissions to AArch64 system registers
bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
ThreadContext *tc);
Fault checkFaultWriteAArch64SysReg(MiscRegIndex reg, HCR hcr,
SCR scr, CPSR cpsr, ThreadContext *tc, const MiscRegOp64 &inst);
// Uses just the scr.ns bit to pre flatten the misc regs. This is useful
// for MCR/MRC instructions