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arch-arm: Streamline RVBAR_EL1/EL2 access permissions

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We don't need to handle RVBAR_EL1 and RVBAR_EL2 separately
every time we read or write a system register.
Instead we can just setup access permissions once at bringup,
based on the highest implemented Exception Level

Change-Id: I19a2cbd783829051766ea45d76a964acc29fe73a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61676
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2022-07-07 17:51:30 +01:00
parent 5f67c7e54d
commit 79cbb0a668
1 changed files with 2 additions and 14 deletions
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16
src/arch/arm/regs/misc.cc
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@@ -731,18 +731,6 @@ canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
if ((reg == MISCREG_SP_EL0) && (tc->readMiscReg(MISCREG_SPSEL) == 0))
return false;
// Check for RVBAR access
if (reg == MISCREG_RVBAR_EL1) {
ExceptionLevel highest_el = ArmSystem::highestEL(tc);
if (highest_el == EL2 || highest_el == EL3)
return false;
}
if (reg == MISCREG_RVBAR_EL2) {
ExceptionLevel highest_el = ArmSystem::highestEL(tc);
if (highest_el == EL3)
return false;
}
bool secure = ArmSystem::haveEL(tc, EL3) && !scr.ns;
bool el2_host = EL2Enabled(tc) && hcr.e2h;
const auto& miscreg_info = lookUpMiscReg[reg].info;
@@ -3294,7 +3282,7 @@ ISA::initializeMiscRegMetadata()
.hypE2H()
.mapsTo(MISCREG_VBAR_NS);
InitReg(MISCREG_RVBAR_EL1)
.allPrivileges().exceptUserMode().writes(0);
.privRead(FullSystem && system->highestEL() == EL1);
InitReg(MISCREG_ISR_EL1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_VBAR_EL2)
@@ -3302,7 +3290,7 @@ ISA::initializeMiscRegMetadata()
.res0(0x7ff)
.mapsTo(MISCREG_HVBAR);
InitReg(MISCREG_RVBAR_EL2)
.mon().hyp().writes(0);
.hypRead(FullSystem && system->highestEL() == EL2);
InitReg(MISCREG_VBAR_EL3)
.mon();
InitReg(MISCREG_RVBAR_EL3)