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misc: Merge branch 'release-staging-v20.1.0.0' into develop

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Change-Id: I8c3277af7903f0b055b26e497139455a03678524
This commit is contained in:
Bobby R. Bruce
2020-09-16 17:16:17 -07:00
parent f2d7005f60 914d6af8a8
commit 9a39ac876e
6 changed files with 16 additions and 22 deletions
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6
configs/common/MemConfig.py
View File

@@ -227,11 +227,15 @@ def config_mem(options, system):
mem_ctrl = m5.objects.MemCtrl(min_writes_per_switch = 8,
static_backend_latency = '4ns',
static_frontend_latency = '4ns')
elif opt_mem_type == "SimpleMemory":
mem_ctrl = m5.objects.SimpleMemory()
else:
mem_ctrl = m5.objects.MemCtrl()
# Hookup the controller to the interface and add to the list
mem_ctrl.dram = dram_intf
if opt_mem_type != "SimpleMemory":
mem_ctrl.dram = dram_intf
mem_ctrls.append(mem_ctrl)
elif opt_nvm_type and (not opt_mem_type or range_iter % 2 == 0):

8
src/arch/arm/isa/insts/neon.isa
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@@ -1452,7 +1452,7 @@ let {{
rCount = 2
eWalkCode = simdEnabledCheckCode + '''
RegVect srcReg1, srcReg2;
BigRegVect destReg = {0};
BigRegVect destReg = {};
'''
for reg in range(rCount):
eWalkCode += '''
@@ -1654,7 +1654,7 @@ let {{
global header_output, exec_output
eWalkCode = simdEnabledCheckCode + '''
RegVect srcReg1;
BigRegVect destReg = {0};
BigRegVect destReg = {};
'''
for reg in range(2):
eWalkCode += '''
@@ -1884,7 +1884,7 @@ let {{
global header_output, exec_output
eWalkCode = simdEnabledCheckCode + '''
RegVect srcRegs;
BigRegVect destReg = {0};
BigRegVect destReg = {};
'''
for reg in range(rCount):
eWalkCode += '''
@@ -2010,7 +2010,7 @@ let {{
global header_output, exec_output
eWalkCode = simdEnabledCheckCode + '''
RegVect srcReg1;
BigRegVect destReg = {0};
BigRegVect destReg = {};
'''
for reg in range(2):
eWalkCode += '''

4
src/arch/arm/isa/insts/neon64.isa
View File

@@ -351,7 +351,7 @@ let {{
global header_output, exec_output
eWalkCode = simd64EnabledCheckCode + '''
RegVect srcReg1;
BigRegVect destReg = {0};
BigRegVect destReg = {};
'''
destReg = 0 if not hi else 2
for reg in range(2):
@@ -632,7 +632,7 @@ let {{
global header_output, exec_output
eWalkCode = simd64EnabledCheckCode + '''
RegVect srcRegs;
BigRegVect destReg = {0};
BigRegVect destReg = {};
'''
for reg in range(rCount):
eWalkCode += '''

2
src/gpu-compute/X86GPUTLB.py
View File

@@ -77,6 +77,6 @@ class TLBCoalescer(ClockedObject):
slave = DeprecatedParam(cpu_side_ports,
'`slave` is now called `cpu_side_ports`')
mem_side_ports = VectorRequestPort("Port on side closer to memory")
master DeprecatedParam(mem_side_ports,
master = DeprecatedParam(mem_side_ports,
'`master` is now called `mem_side_ports`')
disableCoalescing = Param.Bool(False,"Dispable Coalescing")

9
src/mem/ruby/system/GPUCoalescer.cc
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@@ -31,16 +31,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/system/GPUCoalescer.hh"
#include "base/logging.hh"
#include "base/str.hh"
#include "config/the_isa.hh"
#if THE_ISA == X86_ISA
#include "arch/x86/insts/microldstop.hh"
#endif // X86_ISA
#include "mem/ruby/system/GPUCoalescer.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/GPUCoalescer.hh"
#include "debug/MemoryAccess.hh"

9
src/mem/ruby/system/VIPERCoalescer.cc
View File

@@ -31,16 +31,11 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/ruby/system/VIPERCoalescer.hh"
#include "base/logging.hh"
#include "base/str.hh"
#include "config/the_isa.hh"
#if THE_ISA == X86_ISA
#include "arch/x86/insts/microldstop.hh"
#endif // X86_ISA
#include "mem/ruby/system/VIPERCoalescer.hh"
#include "cpu/testers/rubytest/RubyTester.hh"
#include "debug/GPUCoalescer.hh"
#include "debug/MemoryAccess.hh"