From 15faee77ec49b9a0dfebaf7cc02dc11dd7f7285f Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 14 Sep 2020 19:40:42 -0700 Subject: [PATCH 1/4] arm: Use zero initialization for the BigRegVect types. These were being initialized with BigRegVect brv = {0}, which made the compiler complain because there is internal structure. The first element of the union is actually an array, and this was telling it to initialize that array to scalar 0. It was warning about this which was breaking the build. Instead, use zero initlization like BigRegVect brv = {}. This initializes the first element of the union to all zeroes, with all padding bits initialized to zero as well. This satisfies the compiler and avoids a build error. Change-Id: I31e7a8730c538637ff2e0c7fb00a4e12ed05e074 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34575 Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce Tested-by: kokoro --- src/arch/arm/isa/insts/neon.isa | 8 ++++---- src/arch/arm/isa/insts/neon64.isa | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa index c8f8fcd849..6290203e18 100644 --- a/src/arch/arm/isa/insts/neon.isa +++ b/src/arch/arm/isa/insts/neon.isa @@ -1452,7 +1452,7 @@ let {{ rCount = 2 eWalkCode = simdEnabledCheckCode + ''' RegVect srcReg1, srcReg2; - BigRegVect destReg = {0}; + BigRegVect destReg = {}; ''' for reg in range(rCount): eWalkCode += ''' @@ -1654,7 +1654,7 @@ let {{ global header_output, exec_output eWalkCode = simdEnabledCheckCode + ''' RegVect srcReg1; - BigRegVect destReg = {0}; + BigRegVect destReg = {}; ''' for reg in range(2): eWalkCode += ''' @@ -1884,7 +1884,7 @@ let {{ global header_output, exec_output eWalkCode = simdEnabledCheckCode + ''' RegVect srcRegs; - BigRegVect destReg = {0}; + BigRegVect destReg = {}; ''' for reg in range(rCount): eWalkCode += ''' @@ -2010,7 +2010,7 @@ let {{ global header_output, exec_output eWalkCode = simdEnabledCheckCode + ''' RegVect srcReg1; - BigRegVect destReg = {0}; + BigRegVect destReg = {}; ''' for reg in range(2): eWalkCode += ''' diff --git a/src/arch/arm/isa/insts/neon64.isa b/src/arch/arm/isa/insts/neon64.isa index 702c128ccf..f049c3ead2 100644 --- a/src/arch/arm/isa/insts/neon64.isa +++ b/src/arch/arm/isa/insts/neon64.isa @@ -351,7 +351,7 @@ let {{ global header_output, exec_output eWalkCode = simd64EnabledCheckCode + ''' RegVect srcReg1; - BigRegVect destReg = {0}; + BigRegVect destReg = {}; ''' destReg = 0 if not hi else 2 for reg in range(2): @@ -632,7 +632,7 @@ let {{ global header_output, exec_output eWalkCode = simd64EnabledCheckCode + ''' RegVect srcRegs; - BigRegVect destReg = {0}; + BigRegVect destReg = {}; ''' for reg in range(rCount): eWalkCode += ''' From 49a41da96474a6c3b41d3202d24f0be9eb899fbe Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 14 Sep 2020 19:45:13 -0700 Subject: [PATCH 2/4] gpu: Fix a syntax error in X86GPUTLB.py. The recent changes which removed master/slave terminology also accidentally deleted an "=", making the syntax in that file illegal. Change-Id: I50aa945f0f66765db36775380b98a88caff23c13 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34576 Reviewed-by: Bobby R. Bruce Maintainer: Bobby R. Bruce Tested-by: kokoro --- src/gpu-compute/X86GPUTLB.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gpu-compute/X86GPUTLB.py b/src/gpu-compute/X86GPUTLB.py index 45cb962298..fee9b9a9b9 100644 --- a/src/gpu-compute/X86GPUTLB.py +++ b/src/gpu-compute/X86GPUTLB.py @@ -77,6 +77,6 @@ class TLBCoalescer(ClockedObject): slave = DeprecatedParam(cpu_side_ports, '`slave` is now called `cpu_side_ports`') mem_side_ports = VectorRequestPort("Port on side closer to memory") - master DeprecatedParam(mem_side_ports, + master = DeprecatedParam(mem_side_ports, '`master` is now called `mem_side_ports`') disableCoalescing = Param.Bool(False,"Dispable Coalescing") From e5a3584df764bf970f832bda30821de8a758ff4b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 14 Sep 2020 19:46:47 -0700 Subject: [PATCH 3/4] mem-ruby: Remove conditional includes based on THE_ISA in ruby. These were including instruction class definitions from x86 for some reason. There was no code in those .cc files which actually used anything from them, as evidenced by the fact that the GCN3_X86 build still works. No other code in the file was conditionally compiled as of today. Change-Id: I3cef8348fb601dd7af67665cf64bbf514c91c3db Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34577 Reviewed-by: Matthew Poremba Maintainer: Bobby R. Bruce Tested-by: kokoro --- src/mem/ruby/system/GPUCoalescer.cc | 9 ++------- src/mem/ruby/system/VIPERCoalescer.cc | 9 ++------- 2 files changed, 4 insertions(+), 14 deletions(-) diff --git a/src/mem/ruby/system/GPUCoalescer.cc b/src/mem/ruby/system/GPUCoalescer.cc index 03c392f7f6..f5d4f02bdc 100644 --- a/src/mem/ruby/system/GPUCoalescer.cc +++ b/src/mem/ruby/system/GPUCoalescer.cc @@ -31,16 +31,11 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include "mem/ruby/system/GPUCoalescer.hh" + #include "base/logging.hh" #include "base/str.hh" #include "config/the_isa.hh" - -#if THE_ISA == X86_ISA -#include "arch/x86/insts/microldstop.hh" - -#endif // X86_ISA -#include "mem/ruby/system/GPUCoalescer.hh" - #include "cpu/testers/rubytest/RubyTester.hh" #include "debug/GPUCoalescer.hh" #include "debug/MemoryAccess.hh" diff --git a/src/mem/ruby/system/VIPERCoalescer.cc b/src/mem/ruby/system/VIPERCoalescer.cc index a8a3aa952c..82c7f00525 100644 --- a/src/mem/ruby/system/VIPERCoalescer.cc +++ b/src/mem/ruby/system/VIPERCoalescer.cc @@ -31,16 +31,11 @@ * POSSIBILITY OF SUCH DAMAGE. */ +#include "mem/ruby/system/VIPERCoalescer.hh" + #include "base/logging.hh" #include "base/str.hh" #include "config/the_isa.hh" - -#if THE_ISA == X86_ISA -#include "arch/x86/insts/microldstop.hh" - -#endif // X86_ISA -#include "mem/ruby/system/VIPERCoalescer.hh" - #include "cpu/testers/rubytest/RubyTester.hh" #include "debug/GPUCoalescer.hh" #include "debug/MemoryAccess.hh" From 914d6af8a875f472a919fd6619a0a7da7fd78c6d Mon Sep 17 00:00:00 2001 From: Jason Lowe-Power Date: Tue, 15 Sep 2020 17:59:51 -0700 Subject: [PATCH 4/4] configs: Add special case in MemConfig SimpleMemory doesn't implement a full MemCtrl interface. Thus, like the NVM and HMC memories, we need to add a special case to MemConfig.py. The --mem-type command line option now works for SimpleMemory and all of the DRAM interfaces (it does not work for the NVM interfaces, though). Issue-on: https://gem5.atlassian.net/browse/GEM5-777 Change-Id: I6d60649215be324bdd2a104b1976752f936c960e Signed-off-by: Jason Lowe-Power Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/34595 Reviewed-by: Daniel Carvalho Reviewed-by: Nikos Nikoleris Maintainer: Jason Lowe-Power Tested-by: kokoro --- configs/common/MemConfig.py | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py index 941b381d43..8221f85f00 100644 --- a/configs/common/MemConfig.py +++ b/configs/common/MemConfig.py @@ -227,11 +227,15 @@ def config_mem(options, system): mem_ctrl = m5.objects.MemCtrl(min_writes_per_switch = 8, static_backend_latency = '4ns', static_frontend_latency = '4ns') + elif opt_mem_type == "SimpleMemory": + mem_ctrl = m5.objects.SimpleMemory() else: mem_ctrl = m5.objects.MemCtrl() # Hookup the controller to the interface and add to the list - mem_ctrl.dram = dram_intf + if opt_mem_type != "SimpleMemory": + mem_ctrl.dram = dram_intf + mem_ctrls.append(mem_ctrl) elif opt_nvm_type and (not opt_mem_type or range_iter % 2 == 0):