derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

mem-cache: alias to mem::getMasterPort in TLB class

Browse Source 
TLB:getMasterPort is used to obtain the PageWalkMasterPort if present and
hides the BaseTLB::getMasterPort().

The TLB::getMasterPort() is renamed according to the expected behavior.

Change-Id: If4f61189094a706d59805cd10f4f814e5830eda8
Reviewed-on: https://gem5-review.googlesource.com/c/16648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Andrea Mondelli
2019-02-22 11:29:10 -05:00
parent a7eebbfa69
commit 96cc03f90d
6 changed files with 18 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/tlb.cc
View File

@@ -1244,7 +1244,7 @@ TLB::translateComplete(const RequestPtr &req, ThreadContext *tc,
}
BaseMasterPort*
TLB::getMasterPort()
TLB::getTableWalkerMasterPort()
{
return &stage2Mmu->getPort();
}

2
src/arch/arm/tlb.hh
View File

@@ -401,7 +401,7 @@ class TLB : public BaseTLB
*
* @return A pointer to the walker master port
*/
BaseMasterPort* getMasterPort() override;
BaseMasterPort* getTableWalkerMasterPort() override;
// Caching misc register values here.
// Writing to misc registers needs to invalidate them.

3
src/arch/generic/tlb.hh
View File

@@ -58,6 +58,7 @@ class BaseTLB : public MemObject
{}
public:
enum Mode { Read, Write, Execute };
class Translation
@@ -138,7 +139,7 @@ class BaseTLB : public MemObject
*
* @return A pointer to the walker master port or NULL if not present
*/
virtual BaseMasterPort* getMasterPort() { return NULL; }
virtual BaseMasterPort* getTableWalkerMasterPort() { return NULL; }
void memInvalidate() { flushAll(); }
};

2
src/arch/x86/tlb.cc
View File

@@ -512,7 +512,7 @@ TLB::unserialize(CheckpointIn &cp)
}
BaseMasterPort *
TLB::getMasterPort()
TLB::getTableWalkerMasterPort()
{
return &walker->getMasterPort("port");
}

2
src/arch/x86/tlb.hh
View File

@@ -165,7 +165,7 @@ namespace X86ISA
*
* @return A pointer to the walker master port
*/
BaseMasterPort *getMasterPort() override;
BaseMasterPort *getTableWalkerMasterPort() override;
};
}

20
src/cpu/base.cc
View File

@@ -621,10 +621,14 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
ThreadContext::compare(oldTC, newTC);
*/
BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort();
BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort();
BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort();
BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort();
BaseMasterPort *old_itb_port =
oldTC->getITBPtr()->getTableWalkerMasterPort();
BaseMasterPort *old_dtb_port =
oldTC->getDTBPtr()->getTableWalkerMasterPort();
BaseMasterPort *new_itb_port =
newTC->getITBPtr()->getTableWalkerMasterPort();
BaseMasterPort *new_dtb_port =
newTC->getDTBPtr()->getTableWalkerMasterPort();
// Move over any table walker ports if they exist
if (new_itb_port) {
@@ -652,13 +656,13 @@ BaseCPU::takeOverFrom(BaseCPU *oldCPU)
CheckerCPU *newChecker = newTC->getCheckerCpuPtr();
if (oldChecker && newChecker) {
BaseMasterPort *old_checker_itb_port =
oldChecker->getITBPtr()->getMasterPort();
oldChecker->getITBPtr()->getTableWalkerMasterPort();
BaseMasterPort *old_checker_dtb_port =
oldChecker->getDTBPtr()->getMasterPort();
oldChecker->getDTBPtr()->getTableWalkerMasterPort();
BaseMasterPort *new_checker_itb_port =
newChecker->getITBPtr()->getMasterPort();
newChecker->getITBPtr()->getTableWalkerMasterPort();
BaseMasterPort *new_checker_dtb_port =
newChecker->getDTBPtr()->getMasterPort();
newChecker->getDTBPtr()->getTableWalkerMasterPort();
newChecker->getITBPtr()->takeOverFrom(oldChecker->getITBPtr());
newChecker->getDTBPtr()->takeOverFrom(oldChecker->getDTBPtr());