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arch-arm: Fix secure write of SCTLR when EL3 is AArch64

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MiscRegisters are not banked between secure and non-secure mode if EL3
is not implemented or if EL3 is using AArch64 (highestELIs64).  In this
scenario a unique register is used and it is mapped to the NS version
(see snsBankedIndex implementation), so that a secure world read/write
should access the non secure storage.

Change-Id: Ica4182e3cdf4021d2bd1db23e477ce2bbf055926
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9502
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Giacomo Travaglini
2018-03-27 16:22:31 +01:00
parent 0fa5ed40c4
commit 96bba0c50c
1 changed files with 8 additions and 2 deletions
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10
src/arch/arm/isa.cc
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@@ -952,8 +952,14 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
{
DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
scr = readMiscRegNoEffect(MISCREG_SCR);
MiscRegIndex sctlr_idx = (haveSecurity && !scr.ns)
? MISCREG_SCTLR_S : MISCREG_SCTLR_NS;
MiscRegIndex sctlr_idx;
if (haveSecurity && !highestELIs64 && !scr.ns) {
sctlr_idx = MISCREG_SCTLR_S;
} else {
sctlr_idx = MISCREG_SCTLR_NS;
}
SCTLR sctlr = miscRegs[sctlr_idx];
SCTLR new_sctlr = newVal;
new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization;