misc: Adding SingleChannelSimpleMemory.

This change adds SimpleSingleChannelMemory to the components
library.

Change-Id: Id633d207842106a7da8532d3ac64adf022d30d7c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51611
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>

src/python/SConscript

@@ -114,6 +114,7 @@ PySource('gem5.components.memory', 'gem5/components/memory/__init__.py')
 PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py')
 PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
 PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')
+PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
 PySource('gem5.components.memory.dram_interfaces',
     'gem5/components/memory/dram_interfaces/__init__.py')
 PySource('gem5.components.memory.dram_interfaces',

src/python/gem5/components/memory/simple.py

@@ -0,0 +1,84 @@
+# Copyright (c) 2021 The Regents of the University of California
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""Simple memory controllers
+"""
+
+from ...utils.override import overrides
+from m5.util.convert import toMemorySize
+from typing import List, Sequence, Tuple
+from ..boards.abstract_board import AbstractBoard
+from .abstract_memory_system import AbstractMemorySystem
+from m5.objects import AddrRange, MemCtrl, Port, SimpleMemory
+
+class SingleChannelSimpleMemory(AbstractMemorySystem):
+    """A class to implement single channel memory system using SimpleMemory
+
+    This class takes latency, latency variation, and bandwidth and configures
+    a memory with those values. It could be used for studies that do not target
+    memory subsystem design.
+    """
+
+    def __init__(
+        self, latency: str, latency_var: str, bandwidth: str, size: str
+    ):
+        """
+        :param latency: The average of request to response latency.
+        :param latency_var: The variance of request to response latency.
+        :param bandwidth: Combined read and write bandwidth.
+        :param size: Size of the memory.
+        """
+        super().__init__()
+
+        self.module = SimpleMemory(
+            latency=latency, latency_var=latency_var, bandwidth=bandwidth
+        )
+        self._size = toMemorySize(size)
+
+    @overrides(AbstractMemorySystem)
+    def incorporate_memory(self, board: AbstractBoard) -> None:
+        pass
+
+    @overrides(AbstractMemorySystem)
+    def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]:
+        return [(self.module.range, self.module.port)]
+
+    @overrides(AbstractMemorySystem)
+    def get_memory_controllers(self) -> List[MemCtrl]:
+        return [self.module]
+
+    @overrides(AbstractMemorySystem)
+    def get_size(self) -> int:
+        return self._size
+
+    @overrides(AbstractMemorySystem)
+    def set_memory_range(self, ranges: List[AddrRange]) -> None:
+        if len(ranges) != 1 or ranges[0].size() != self._size:
+            raise Exception(
+                "Simple single channel memory controller requires a single "
+                "range which matches the memory's size."
+            )
+        self.module.range = ranges[0]