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misc: Updating AbstractGeneratorCore

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This change updates AbstractGeneratorCore so that it uses a
PortTerminator instead of a dummy PyTrafficGen. This PortTerminator
will be used to connect to icache, and walker ports.

Change-Id: Ic744003c3e633592449ec7d209e4fbb5242f11fa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/51610
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Mahyar Samani
2021-10-13 16:36:08 -07:00
parent b22c0183cf
commit df6eca6036
1 changed files with 8 additions and 7 deletions
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15
src/python/gem5/components/processors/abstract_generator_core.py
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@@ -25,7 +25,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects import Port, PyTrafficGen
from m5.objects import Port, PortTerminator
from ...utils.override import overrides
from .cpu_types import CPUTypes
@@ -52,24 +52,25 @@ class AbstractGeneratorCore(AbstractCore):
# TODO: Remove the CPU Type parameter. This not needed.
# Jira issue here: https://gem5.atlassian.net/browse/GEM5-1031
super(AbstractGeneratorCore, self).__init__(CPUTypes.TIMING)
self.dummy_generator = PyTrafficGen()
self.port_end = PortTerminator()
@overrides(AbstractCore)
def connect_icache(self, port: Port) -> None:
"""
Generator cores only have one request port which we will connect to
the data cache not the icache. Just connect the icache to the dummy
generator here.
the data cache not the icache. Just connect the icache to the
PortTerminator here.
"""
self.dummy_generator.port = port
self.port_end.req_ports = port
@overrides(AbstractCore)
def connect_walker_ports(self, port1: Port, port2: Port) -> None:
"""
Since generator cores are not used in full system mode, no need to
connect them to walker ports. Just pass here.
connect them to walker ports. connect them to PortTerminator here.
"""
pass
self.port_end.req_ports = port1
self.port_end.req_ports = port2
@overrides(AbstractCore)
def set_workload(self, process: "Process") -> None: