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configs: Replace master/slave terminology from configs scripts

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Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I6a1a06abeca1621efb378c400c5b24b33a7a3727
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52866
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-11-09 10:21:58 +00:00
parent 65c32dc491
commit 8a9ea974ee
24 changed files with 168 additions and 154 deletions
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8
configs/common/GPUTLBConfig.py
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@@ -136,7 +136,7 @@ def config_tlb_hierarchy(options, system, shader_idx):
#===========================================================
# Specify the TLB hierarchy (i.e., port connections)
# All TLBs but the last level TLB need to have a memSidePort (master)
# All TLBs but the last level TLB need to have a memSidePort
#===========================================================
# Each TLB is connected with its Coalescer through a single port.
@@ -152,7 +152,7 @@ def config_tlb_hierarchy(options, system, shader_idx):
system.%s_tlb[%d].cpu_side_ports[0]' % \
(name, index, name, index))
# Connect the cpuSidePort (slave) of all the coalescers in level 1
# Connect the cpuSidePort of all the coalescers in level 1
# < Modify here if you want a different configuration >
for TLB_type in L1:
name = TLB_type['name']
@@ -188,8 +188,8 @@ def config_tlb_hierarchy(options, system, shader_idx):
(shader_idx, index, scalar_tlb_index,
scalar_tlb_port_id))
# Connect the memSidePorts (masters) of all the TLBs with the
# cpuSidePorts (slaves) of the Coalescers of the next level
# Connect the memSidePorts of all the TLBs with the
# cpuSidePorts of the Coalescers of the next level
# < Modify here if you want a different configuration >
# L1 <-> L2
l2_coalescer_index = 0