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configs: Replace master/slave terminology from configs scripts

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Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I6a1a06abeca1621efb378c400c5b24b33a7a3727
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52866
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-11-09 10:21:58 +00:00
parent 65c32dc491
commit 8a9ea974ee
24 changed files with 168 additions and 154 deletions
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4
configs/common/CacheConfig.py
View File

@@ -122,8 +122,8 @@ def config_cache(options, system):
**_get_cache_opts('l2', options))
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
system.l2.cpu_side = system.tol2bus.mem_side_ports
system.l2.mem_side = system.membus.cpu_side_ports
if options.memchecker:
system.memchecker = MemChecker()

56
configs/common/FSConfig.py
View File

@@ -120,11 +120,11 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
self.t1000.attachIO(self.iobus)
self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
AddrRange(Addr('2GB'), size ='256MB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = self.membus.mem_side_ports
self.disk0 = CowMmDisk()
self.disk0.childImage(mdesc.disks()[0])
self.disk0.pio = self.iobus.master
self.disk0.pio = self.iobus.mem_side_ports
# The puart0 and hvuart are placed on the IO bus, so create ranges
# for them. The remaining IO range is rather fragmented, so poke
@@ -160,12 +160,12 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
self.partition_desc = SimpleMemory(image_file=binary('1up-md.bin'),
range=AddrRange(0x1f12000000, size='8kB'))
self.rom.port = self.membus.master
self.nvram.port = self.membus.master
self.hypervisor_desc.port = self.membus.master
self.partition_desc.port = self.membus.master
self.rom.port = self.membus.mem_side_ports
self.nvram.port = self.membus.mem_side_ports
self.hypervisor_desc.port = self.membus.mem_side_ports
self.partition_desc.port = self.membus.mem_side_ports
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
self.workload = workload
@@ -189,10 +189,10 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
self.iobus = IOXBar()
if not ruby:
self.bridge = Bridge(delay='50ns')
self.bridge.master = self.iobus.slave
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
self.bridge.slave = self.membus.master
self.bridge.cpu_side_port = self.membus.mem_side_ports
self.mem_mode = mem_mode
@@ -299,13 +299,13 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
# I/O traffic enters iobus
self.external_io = ExternalMaster(port_data="external_io",
port_type=external_memory)
self.external_io.port = self.iobus.slave
self.external_io.port = self.iobus.cpu_side_ports
# Ensure iocache only receives traffic destined for (actual) memory.
self.iocache = ExternalSlave(port_data="iocache",
port_type=external_memory,
addr_ranges=self.mem_ranges)
self.iocache.port = self.iobus.master
self.iocache.port = self.iobus.mem_side_ports
# Let system_port get to nvmem and nothing else.
self.bridge.ranges = [self.realview.nvmem.range]
@@ -336,7 +336,7 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
attach_9p(self.realview, self.iobus)
if not ruby:
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
if ruby:
if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
@@ -362,15 +362,15 @@ def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.mem_ranges = [AddrRange('1GB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = self.membus.mem_side_ports
self.disks = makeCowDisks(mdesc.disks())
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.master
self.malta.ide.dma = self.iobus.slave
self.malta.ethernet.pio = self.iobus.master
self.malta.ethernet.dma = self.iobus.slave
self.malta.ide.pio = self.iobus.mem_side_ports
self.malta.ide.dma = self.iobus.cpu_side_ports
self.malta.ethernet.pio = self.iobus.mem_side_ports
self.malta.ethernet.dma = self.iobus.cpu_side_ports
self.simple_disk = SimpleDisk(disk=RawDiskImage(
image_file = mdesc.disks()[0], read_only = True))
self.mem_mode = mem_mode
@@ -380,7 +380,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
cmdline = 'root=/dev/hda1 console=ttyS0'
self.workload = KernelWorkload(command_line=fillInCmdline(mdesc, cmdline))
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
return self
@@ -400,8 +400,8 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# North Bridge
x86_sys.iobus = IOXBar()
x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
x86_sys.bridge.mem_side_port = x86_sys.iobus.cpu_side_ports
x86_sys.bridge.cpu_side_port = x86_sys.membus.mem_side_ports
# Allow the bridge to pass through:
# 1) kernel configured PCI device memory map address: address range
# [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
@@ -420,8 +420,8 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# Create a bridge from the IO bus to the memory bus to allow access to
# the local APIC (two pages)
x86_sys.apicbridge = Bridge(delay='50ns')
x86_sys.apicbridge.slave = x86_sys.iobus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.apicbridge.cpu_side_port = x86_sys.iobus.mem_side_ports
x86_sys.apicbridge.mem_side_port = x86_sys.membus.cpu_side_ports
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
numCPUs * APIC_range_size
@@ -430,7 +430,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# connect the io bus
x86_sys.pc.attachIO(x86_sys.iobus)
x86_sys.system_port = x86_sys.membus.slave
x86_sys.system_port = x86_sys.membus.cpu_side_ports
def connectX86RubySystem(x86_sys):
# North Bridge
@@ -646,13 +646,13 @@ def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = self.membus.mem_side_ports
# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO space
IO_address_space_base = 0x00FF000000000000
self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
return self
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):

8
configs/common/GPUTLBConfig.py
View File

@@ -136,7 +136,7 @@ def config_tlb_hierarchy(options, system, shader_idx):
#===========================================================
# Specify the TLB hierarchy (i.e., port connections)
# All TLBs but the last level TLB need to have a memSidePort (master)
# All TLBs but the last level TLB need to have a memSidePort
#===========================================================
# Each TLB is connected with its Coalescer through a single port.
@@ -152,7 +152,7 @@ def config_tlb_hierarchy(options, system, shader_idx):
system.%s_tlb[%d].cpu_side_ports[0]' % \
(name, index, name, index))
# Connect the cpuSidePort (slave) of all the coalescers in level 1
# Connect the cpuSidePort of all the coalescers in level 1
# < Modify here if you want a different configuration >
for TLB_type in L1:
name = TLB_type['name']
@@ -188,8 +188,8 @@ def config_tlb_hierarchy(options, system, shader_idx):
(shader_idx, index, scalar_tlb_index,
scalar_tlb_port_id))
# Connect the memSidePorts (masters) of all the TLBs with the
# cpuSidePorts (slaves) of the Coalescers of the next level
# Connect the memSidePorts of all the TLBs with the
# cpuSidePorts of the Coalescers of the next level
# < Modify here if you want a different configuration >
# L1 <-> L2
l2_coalescer_index = 0

76
configs/common/HMC.py
View File

@@ -356,25 +356,25 @@ def config_hmc_host_ctrl(opt, system):
mb = system.membus
for i in range(opt.num_links_controllers):
if opt.enable_global_monitor:
mb.master = hh.lmonitor[i].slave
hh.lmonitor[i].master = hh.seriallink[i].slave
mb.mem_side_ports = hh.lmonitor[i].cpu_side_port
hh.lmonitor[i].mem_side_port = hh.seriallink[i].cpu_side_port
else:
mb.master = hh.seriallink[i].slave
mb.mem_side_ports = hh.seriallink[i].cpu_side_port
if opt.arch == "mixed":
mb = system.membus
if opt.enable_global_monitor:
mb.master = hh.lmonitor[0].slave
hh.lmonitor[0].master = hh.seriallink[0].slave
mb.master = hh.lmonitor[1].slave
hh.lmonitor[1].master = hh.seriallink[1].slave
mb.mem_side_ports = hh.lmonitor[0].cpu_side_port
hh.lmonitor[0].mem_side_port = hh.seriallink[0].cpu_side_port
mb.mem_side_ports = hh.lmonitor[1].cpu_side_port
hh.lmonitor[1].mem_side_port = hh.seriallink[1].cpu_side_port
else:
mb.master = hh.seriallink[0].slave
mb.master = hh.seriallink[1].slave
mb.mem_side_ports = hh.seriallink[0].cpu_side_port
mb.mem_side_ports = hh.seriallink[1].cpu_side_port
if opt.arch == "same":
for i in range(opt.num_links_controllers):
if opt.enable_global_monitor:
hh.lmonitor[i].master = hh.seriallink[i].slave
hh.lmonitor[i].mem_side_port = hh.seriallink[i].cpu_side_port
return system
@@ -412,11 +412,13 @@ def config_hmc_dev(opt, system, hmc_host):
# Attach 4 serial link to 4 crossbar/s
for i in range(opt.num_serial_links):
if opt.enable_link_monitor:
system.hmc_host.seriallink[i].master = \
system.hmc_dev.lmonitor[i].slave
system.hmc_dev.lmonitor[i].master = system.hmc_dev.xbar[i].slave
system.hmc_host.seriallink[i].mem_side_port = \
system.hmc_dev.lmonitor[i].cpu_side_port
system.hmc_dev.lmonitor[i].mem_side_port = \
system.hmc_dev.xbar[i].cpu_side_ports
else:
system.hmc_host.seriallink[i].master = system.hmc_dev.xbar[i].slave
system.hmc_host.seriallink[i].mem_side_port = \
system.hmc_dev.xbar[i].cpu_side_ports
# Connecting xbar with each other for request arriving at the wrong xbar,
# then it will be forward to correct xbar. Bridge is used to connect xbars
@@ -432,7 +434,7 @@ def config_hmc_dev(opt, system, hmc_host):
it = iter(list(range(len(system.hmc_dev.buffers))))
# necesarry to add system_port to one of the xbar
system.system_port = system.hmc_dev.xbar[3].slave
system.system_port = system.hmc_dev.xbar[3].cpu_side_ports
# iterate over all the crossbars and connect them as required
for i in range(numx):
@@ -448,10 +450,10 @@ def config_hmc_dev(opt, system, hmc_host):
(j + 1) * int(opt.mem_chunk)]
# Connect the bridge between corssbars
system.hmc_dev.xbar[i].master = system.hmc_dev.buffers[
index].slave
system.hmc_dev.buffers[
index].master = system.hmc_dev.xbar[j].slave
system.hmc_dev.xbar[i].mem_side_ports = \
system.hmc_dev.buffers[index].cpu_side_port
system.hmc_dev.buffers[index].mem_side_port = \
system.hmc_dev.xbar[j].cpu_side_ports
else:
# Don't connect the xbar to itself
pass
@@ -460,25 +462,37 @@ def config_hmc_dev(opt, system, hmc_host):
# can only direct traffic to it local vaults
if opt.arch == "mixed":
system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4])
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer30.slave
system.hmc_dev.buffer30.master = system.hmc_dev.xbar[0].slave
system.hmc_dev.xbar[3].mem_side_ports = \
system.hmc_dev.buffer30.cpu_side_port
system.hmc_dev.buffer30.mem_side_port = \
system.hmc_dev.xbar[0].cpu_side_ports
system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8])
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer31.slave
system.hmc_dev.buffer31.master = system.hmc_dev.xbar[1].slave
system.hmc_dev.xbar[3].mem_side_ports = \
system.hmc_dev.buffer31.cpu_side_port
system.hmc_dev.buffer31.mem_side_port = \
system.hmc_dev.xbar[1].cpu_side_ports
system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12])
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer32.slave
system.hmc_dev.buffer32.master = system.hmc_dev.xbar[2].slave
system.hmc_dev.xbar[3].mem_side_ports = \
system.hmc_dev.buffer32.cpu_side_port
system.hmc_dev.buffer32.mem_side_port = \
system.hmc_dev.xbar[2].cpu_side_ports
system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4])
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer20.slave
system.hmc_dev.buffer20.master = system.hmc_dev.xbar[0].slave
system.hmc_dev.xbar[2].mem_side_ports = \
system.hmc_dev.buffer20.cpu_side_port
system.hmc_dev.buffer20.mem_side_port = \
system.hmc_dev.xbar[0].cpu_side_ports
system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8])
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer21.slave
system.hmc_dev.buffer21.master = system.hmc_dev.xbar[1].slave
system.hmc_dev.xbar[2].mem_side_ports = \
system.hmc_dev.buffer21.cpu_side_port
system.hmc_dev.buffer21.mem_side_port = \
system.hmc_dev.xbar[1].cpu_side_ports
system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer23.slave
system.hmc_dev.buffer23.master = system.hmc_dev.xbar[3].slave
system.hmc_dev.xbar[2].mem_side_ports = \
system.hmc_dev.buffer23.cpu_side_port
system.hmc_dev.buffer23.mem_side_port = \
system.hmc_dev.xbar[3].cpu_side_ports

2
configs/common/MemConfig.py
View File

@@ -156,7 +156,7 @@ def config_mem(options, system):
if opt_external_memory_system:
subsystem.external_memory = m5.objects.ExternalSlave(
port_type=opt_external_memory_system,
port_data="init_mem0", port=xbar.master,
port_data="init_mem0", port=xbar.mem_side_ports,
addr_ranges=system.mem_ranges)
subsystem.workload.addr_check = False
return

16
configs/dram/lat_mem_rd.py
View File

@@ -250,7 +250,7 @@ system.monitor = CommMonitor()
system.monitor.footprint = MemFootprintProbe()
# connect the traffic generator to the system
system.tgen.port = system.monitor.slave
system.tgen.port = system.monitor.cpu_side_port
# create the actual cache hierarchy, for now just go with something
# basic to explore some of the options
@@ -270,23 +270,23 @@ class L3Cache(Cache):
# note that everything is in the same clock domain, 2.0 GHz as
# specified above
system.l1cache = L1_DCache(size = '64kB')
system.monitor.master = system.l1cache.cpu_side
system.monitor.mem_side_port = system.l1cache.cpu_side
system.l2cache = L2Cache(size = '512kB', writeback_clean = True)
system.l2cache.xbar = L2XBar()
system.l1cache.mem_side = system.l2cache.xbar.slave
system.l2cache.cpu_side = system.l2cache.xbar.master
system.l1cache.mem_side = system.l2cache.xbar.cpu_side_ports
system.l2cache.cpu_side = system.l2cache.xbar.mem_side_ports
# make the L3 mostly exclusive, and correspondingly ensure that the L2
# writes back also clean lines to the L3
system.l3cache = L3Cache(size = '4MB', clusivity = 'mostly_excl')
system.l3cache.xbar = L2XBar()
system.l2cache.mem_side = system.l3cache.xbar.slave
system.l3cache.cpu_side = system.l3cache.xbar.master
system.l3cache.mem_side = system.membus.slave
system.l2cache.mem_side = system.l3cache.xbar.cpu_side_ports
system.l3cache.cpu_side = system.l3cache.xbar.mem_side_ports
system.l3cache.mem_side = system.membus.cpu_side_ports
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
# every period, dump and reset all stats
periodicStatDump(period)

6
configs/dram/low_power_sweep.py
View File

@@ -223,11 +223,11 @@ system.tgen = TrafficGen(config_file = cfg_file_path)
system.monitor = CommMonitor()
# connect the traffic generator to the bus via a communication monitor
system.tgen.port = system.monitor.slave
system.monitor.master = system.membus.slave
system.tgen.port = system.monitor.cpu_side_port
system.monitor.mem_side_port = system.membus.cpu_side_ports
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
# every period, dump and reset all stats
periodicStatDump(period)

6
configs/dram/sweep.py
View File

@@ -158,11 +158,11 @@ system.tgen = PyTrafficGen()
system.monitor = CommMonitor()
# connect the traffic generator to the bus via a communication monitor
system.tgen.port = system.monitor.slave
system.monitor.master = system.membus.slave
system.tgen.port = system.monitor.cpu_side_port
system.monitor.mem_side_port = system.membus.cpu_side_ports
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
# every period, dump and reset all stats
periodicStatDump(period)

2
configs/example/etrace_replay.py
View File

@@ -110,7 +110,7 @@ system.cpu.dataTraceFile=args.data_trace_file
# Configure the classic memory system args
MemClass = Simulation.setMemClass(args)
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
CacheConfig.config_cache(args, system)
MemConfig.config_mem(args, system)

16
configs/example/fs.py
View File

@@ -148,7 +148,7 @@ def build_test_system(np):
# Connect the ruby io port to the PIO bus,
# assuming that there is just one such port.
test_sys.iobus.master = test_sys.ruby._io_port.slave
test_sys.iobus.mem_side_ports = test_sys.ruby._io_port.in_ports
for (i, cpu) in enumerate(test_sys.cpu):
#
@@ -164,12 +164,12 @@ def build_test_system(np):
if args.caches or args.l2cache:
# By default the IOCache runs at the system clock
test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
test_sys.iocache.cpu_side = test_sys.iobus.master
test_sys.iocache.mem_side = test_sys.membus.slave
test_sys.iocache.cpu_side = test_sys.iobus.mem_side_ports
test_sys.iocache.mem_side = test_sys.membus.cpu_side_ports
elif not args.external_memory_system:
test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
test_sys.iobridge.slave = test_sys.iobus.master
test_sys.iobridge.master = test_sys.membus.slave
test_sys.iobridge.cpu_side_port = test_sys.iobus.mem_side_ports
test_sys.iobridge.mem_side_port = test_sys.membus.cpu_side_ports
# Sanity check
if args.simpoint_profile:
@@ -272,15 +272,15 @@ def build_drive_system(np):
drive_sys.iobridge = Bridge(delay='50ns',
ranges = drive_sys.mem_ranges)
drive_sys.iobridge.slave = drive_sys.iobus.master
drive_sys.iobridge.master = drive_sys.membus.slave
drive_sys.iobridge.cpu_side_port = drive_sys.iobus.mem_side_ports
drive_sys.iobridge.mem_side_port = drive_sys.membus.cpu_side_ports
# Create the appropriate memory controllers and connect them to the
# memory bus
drive_sys.mem_ctrls = [DriveMemClass(range = r)
for r in drive_sys.mem_ranges]
for i in range(len(drive_sys.mem_ctrls)):
drive_sys.mem_ctrls[i].port = drive_sys.membus.master
drive_sys.mem_ctrls[i].port = drive_sys.membus.mem_side_ports
drive_sys.init_param = args.init_param

2
configs/example/garnet_synth_traffic.py
View File

@@ -121,7 +121,7 @@ for ruby_port in system.ruby._cpu_ports:
#
# Tie the cpu test ports to the ruby cpu port
#
cpus[i].test = ruby_port.slave
cpus[i].test = ruby_port.in_ports
i += 1
# -----------------------

8
configs/example/hmc_hello.py
View File

@@ -47,7 +47,7 @@ HMC.add_options(parser)
options = parser.parse_args()
# create the system we are going to simulate
system = System()
# use timing mode for the interaction between master-slave ports
# use timing mode for the interaction between requestor-responder ports
system.mem_mode = 'timing'
# set the clock fequency of the system
clk = '1GHz'
@@ -58,13 +58,13 @@ system.cpu = TimingSimpleCPU()
# config memory system
MemConfig.config_mem(options, system)
# hook the CPU ports up to the membus
system.cpu.icache_port = system.membus.slave
system.cpu.dcache_port = system.membus.slave
system.cpu.icache_port = system.membus.cpu_side_ports
system.cpu.dcache_port = system.membus.cpu_side_ports
# create the interrupt controller for the CPU and connect to the membus
system.cpu.createInterruptController()
# connect special port in the system to the membus. This port is a
# functional-only port to allow the system to read and write memory.
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
# get ISA for the binary to run.
isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
# run 'hello' and use the compiled ISA to find the binary

26
configs/example/hmctest.py
View File

@@ -48,7 +48,7 @@ def add_options(parser):
def build_system(options):
# create the system we are going to simulate
system = System()
# use timing mode for the interaction between master-slave ports
# use timing mode for the interaction between requestor-responder ports
system.mem_mode = 'timing'
# set the clock fequency of the system
clk = '100GHz'
@@ -62,30 +62,30 @@ def build_system(options):
# Connect the traffic generatiors
if options.arch == "distributed":
for i in range(options.num_tgen):
system.tgen[i].port = system.membus.slave
system.tgen[i].port = system.membus.cpu_side_ports
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
if options.arch == "mixed":
for i in range(int(options.num_tgen/2)):
system.tgen[i].port = system.membus.slave
system.tgen[i].port = system.membus.cpu_side_ports
hh = system.hmc_host
if options.enable_global_monitor:
system.tgen[2].port = hh.lmonitor[2].slave
hh.lmonitor[2].master = hh.seriallink[2].slave
system.tgen[3].port = hh.lmonitor[3].slave
hh.lmonitor[3].master = hh.seriallink[3].slave
system.tgen[2].port = hh.lmonitor[2].cpu_side_port
hh.lmonitor[2].mem_side_port = hh.seriallink[2].cpu_side_port
system.tgen[3].port = hh.lmonitor[3].cpu_side_port
hh.lmonitor[3].mem_side_port = hh.seriallink[3].cpu_side_port
else:
system.tgen[2].port = hh.seriallink[2].slave
system.tgen[3].port = hh.seriallink[3].slave
system.tgen[2].port = hh.seriallink[2].cpu_side_port
system.tgen[3].port = hh.seriallink[3].cpu_side_port
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
if options.arch == "same":
hh = system.hmc_host
for i in range(options.num_links_controllers):
if options.enable_global_monitor:
system.tgen[i].port = hh.lmonitor[i].slave
system.tgen[i].port = hh.lmonitor[i].cpu_side_port
else:
system.tgen[i].port = hh.seriallink[i].slave
system.tgen[i].port = hh.seriallink[i].cpu_side_port
# set up the root SimObject
root = Root(full_system=False, system=system)
return root

24
configs/example/memcheck.py
View File

@@ -251,7 +251,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
xbar = L2XBar(width = 32)
subsys.xbar = xbar
if next_cache:
xbar.master = next_cache.cpu_side
xbar.mem_side_ports = next_cache.cpu_side
# Create and connect the caches, both the ones fanning out
# to create the tree, and the ones used to connect testers
@@ -261,12 +261,12 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
subsys.cache = tester_caches + tree_caches
for cache in tree_caches:
cache.mem_side = xbar.slave
cache.mem_side = xbar.cpu_side_ports
make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
for tester, checker, cache in zip(testers, checkers, tester_caches):
tester.port = checker.slave
checker.master = cache.cpu_side
cache.mem_side = xbar.slave
tester.port = checker.cpu_side_port
checker.mem_side_port = cache.cpu_side
cache.mem_side = xbar.cpu_side_ports
else:
if not next_cache:
print("Error: No next-level cache at top level")
@@ -276,21 +276,21 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
# Create a crossbar and add it to the subsystem
xbar = L2XBar(width = 32)
subsys.xbar = xbar
xbar.master = next_cache.cpu_side
xbar.mem_side_ports = next_cache.cpu_side
for tester, checker in zip(testers, checkers):
tester.port = checker.slave
checker.master = xbar.slave
tester.port = checker.cpu_side_port
checker.mem_side_port = xbar.cpu_side_ports
else:
# Single tester
testers[0].port = checkers[0].slave
checkers[0].master = next_cache.cpu_side
testers[0].port = checkers[0].cpu_side_port
checkers[0].mem_side_port = next_cache.cpu_side
# Top level call to create the cache hierarchy, bottom up
make_cache_level(cachespec, cache_proto, len(cachespec), None)
# Connect the lowest level crossbar to the memory
last_subsys = getattr(system, 'l%dsubsys0' % len(cachespec))
last_subsys.xbar.master = system.physmem.port
last_subsys.xbar.mem_side_ports = system.physmem.port
last_subsys.xbar.point_of_coherency = True
root = Root(full_system = False, system = system)
@@ -301,7 +301,7 @@ else:
# The system port is never used in the tester so merely connect it
# to avoid problems
root.system.system_port = last_subsys.xbar.slave
root.system.system_port = last_subsys.xbar.cpu_side_ports
# Instantiate configuration
m5.instantiate()

16
configs/example/memtest.py
View File

@@ -254,7 +254,7 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
xbar = L2XBar()
subsys.xbar = xbar
if next_cache:
xbar.master = next_cache.cpu_side
xbar.mem_side_ports = next_cache.cpu_side
# Create and connect the caches, both the ones fanning out
# to create the tree, and the ones used to connect testers
@@ -264,11 +264,11 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
subsys.cache = tester_caches + tree_caches
for cache in tree_caches:
cache.mem_side = xbar.slave
cache.mem_side = xbar.cpu_side_ports
make_cache_level(ncaches[1:], prototypes[1:], level - 1, cache)
for tester, cache in zip(testers, tester_caches):
tester.port = cache.cpu_side
cache.mem_side = xbar.slave
cache.mem_side = xbar.cpu_side_ports
else:
if not next_cache:
print("Error: No next-level cache at top level")
@@ -278,9 +278,9 @@ def make_cache_level(ncaches, prototypes, level, next_cache):
# Create a crossbar and add it to the subsystem
xbar = L2XBar()
subsys.xbar = xbar
xbar.master = next_cache.cpu_side
xbar.mem_side_ports = next_cache.cpu_side
for tester in testers:
tester.port = xbar.slave
tester.port = xbar.cpu_side_ports
else:
# Single tester
testers[0].port = next_cache.cpu_side
@@ -297,10 +297,10 @@ if args.noncoherent_cache:
data_latency = 10, sequential_access = True,
response_latency = 20, tgts_per_mshr = 8,
mshrs = 64)
last_subsys.xbar.master = system.llc.cpu_side
last_subsys.xbar.mem_side_ports = system.llc.cpu_side
system.llc.mem_side = system.physmem.port
else:
last_subsys.xbar.master = system.physmem.port
last_subsys.xbar.mem_side_ports = system.physmem.port
root = Root(full_system = False, system = system)
if args.atomic:
@@ -310,7 +310,7 @@ else:
# The system port is never used in the tester so merely connect it
# to avoid problems
root.system.system_port = last_subsys.xbar.slave
root.system.system_port = last_subsys.xbar.cpu_side_ports
# Instantiate configuration
m5.instantiate()

8
configs/example/read_config.py
View File

@@ -273,7 +273,7 @@ class ConfigManager(object):
def gather_port_connections(self, object_name, obj):
"""Gather all the port-to-port connections from the named object.
Returns a list of (PortConnection, PortConnection) with unordered
(wrt. master/slave) connection information"""
(wrt. requestor/responder) connection information"""
if object_name == 'Null':
return NULL
@@ -292,8 +292,8 @@ class ConfigManager(object):
def bind_ports(self, connections):
"""Bind all ports from the given connection list. Note that the
connection list *must* list all connections with both (slave,master)
and (master,slave) orderings"""
connection list *must* list all connections with both
(responder,requestor) and (requestor,responder) orderings"""
# Markup a dict of how many connections are made to each port.
# This will be used to check that the next-to-be-made connection
@@ -312,7 +312,7 @@ class ConfigManager(object):
(port.object_name, port.port_name)] += 1
# Step through the sorted connections. Exactly one of
# each (slave,master) and (master,slave) pairs will be
# each (responder,requestor) and (requestor,responder) pairs will be
# bindable because the connections are sorted.
# For example: port_bind_indices
# left right left right

2
configs/example/ruby_direct_test.py
View File

@@ -111,7 +111,7 @@ for ruby_port in system.ruby._cpu_ports:
#
# Tie the ruby tester ports to the ruby cpu ports
#
system.cpu.cpuPort = ruby_port.slave
system.cpu.cpuPort = ruby_port.in_ports
# -----------------------
# run simulation

2
configs/example/ruby_mem_test.py
View File

@@ -133,7 +133,7 @@ for (i, cpu) in enumerate(cpus):
#
# Tie the cpu memtester ports to the correct system ports
#
cpu.port = system.ruby._cpu_ports[i].slave
cpu.port = system.ruby._cpu_ports[i].in_ports
#
# Since the memtester is incredibly bursty, increase the deadlock

6
configs/example/ruby_random_test.py
View File

@@ -126,11 +126,11 @@ for ruby_port in system.ruby._cpu_ports:
# Tie the ruby tester ports to the ruby cpu read and write ports
#
if ruby_port.support_data_reqs and ruby_port.support_inst_reqs:
tester.cpuInstDataPort = ruby_port.slave
tester.cpuInstDataPort = ruby_port.in_ports
elif ruby_port.support_data_reqs:
tester.cpuDataPort = ruby_port.slave
tester.cpuDataPort = ruby_port.in_ports
elif ruby_port.support_inst_reqs:
tester.cpuInstPort = ruby_port.slave
tester.cpuInstPort = ruby_port.in_ports
# Do not automatically retry stalled Ruby requests
ruby_port.no_retry_on_stall = True

2
configs/example/se.py
View File

@@ -257,7 +257,7 @@ if args.ruby:
else:
MemClass = Simulation.setMemClass(args)
system.membus = SystemXBar()
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
CacheConfig.config_cache(args, system)
MemConfig.config_mem(args, system)
config_filesystem(system, args)

6
configs/nvm/sweep.py
View File

@@ -154,11 +154,11 @@ system.tgen = PyTrafficGen()
system.monitor = CommMonitor()
# connect the traffic generator to the bus via a communication monitor
system.tgen.port = system.monitor.slave
system.monitor.master = system.membus.slave
system.tgen.port = system.monitor.cpu_side_port
system.monitor.mem_side_port = system.membus.cpu_side_ports
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
# every period, dump and reset all stats
periodicStatDump(period)

6
configs/nvm/sweep_hybrid.py
View File

@@ -188,11 +188,11 @@ system.tgen = PyTrafficGen()
system.monitor = CommMonitor()
# connect the traffic generator to the bus via a communication monitor
system.tgen.port = system.monitor.slave
system.monitor.master = system.membus.slave
system.tgen.port = system.monitor.cpu_side_port
system.monitor.mem_side_port = system.membus.cpu_side_ports
# connect the system port even if it is not used in this example
system.system_port = system.membus.slave
system.system_port = system.membus.cpu_side_ports
# every period, dump and reset all stats
periodicStatDump(period)

14
configs/splash2/cluster.py
View File

@@ -213,19 +213,19 @@ system.l2 = L2(size = args.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
system.physmem.port = system.membus.master
system.l2.cpu_side = system.toL2bus.slave
system.l2.mem_side = system.membus.master
system.physmem.port = system.membus.mem_side_ports
system.l2.cpu_side = system.toL2bus.cpu_side_ports
system.l2.mem_side = system.membus.mem_side_ports
# ----------------------
# Connect the L2 cache and clusters together
# ----------------------
for cluster in clusters:
cluster.l1.cpu_side = cluster.clusterbus.master
cluster.l1.mem_side = system.toL2bus.slave
cluster.l1.cpu_side = cluster.clusterbus.mem_side_ports
cluster.l1.mem_side = system.toL2bus.cpu_side_ports
for cpu in cluster.cpus:
cpu.icache_port = cluster.clusterbus.slave
cpu.dcache_port = cluster.clusterbus.slave
cpu.icache_port = cluster.clusterbus.cpu_side_ports
cpu.dcache_port = cluster.clusterbus.cpu_side_ports
# ----------------------
# Define the root

8
configs/splash2/run.py
View File

@@ -198,10 +198,10 @@ system.l2 = L2(size = args.l2size, assoc = 8)
# Connect the L2 cache and memory together
# ----------------------
system.physmem.port = system.membus.master
system.l2.cpu_side = system.toL2bus.master
system.l2.mem_side = system.membus.slave
system.system_port = system.membus.slave
system.physmem.port = system.membus.mem_side_ports
system.l2.cpu_side = system.toL2bus.mem_side_ports
system.l2.mem_side = system.membus.cpu_side_ports
system.system_port = system.membus.cpu_side_ports
# ----------------------
# Connect the L2 cache and clusters together