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configs: Replace master/slave terminology from configs scripts

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Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I6a1a06abeca1621efb378c400c5b24b33a7a3727
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52866
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2021-11-09 10:21:58 +00:00
parent 65c32dc491
commit 8a9ea974ee
24 changed files with 168 additions and 154 deletions
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4
configs/common/CacheConfig.py
View File

@@ -122,8 +122,8 @@ def config_cache(options, system):
**_get_cache_opts('l2', options))
system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
system.l2.cpu_side = system.tol2bus.master
system.l2.mem_side = system.membus.slave
system.l2.cpu_side = system.tol2bus.mem_side_ports
system.l2.mem_side = system.membus.cpu_side_ports
if options.memchecker:
system.memchecker = MemChecker()

56
configs/common/FSConfig.py
View File

@@ -120,11 +120,11 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
self.t1000.attachIO(self.iobus)
self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
AddrRange(Addr('2GB'), size ='256MB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = self.membus.mem_side_ports
self.disk0 = CowMmDisk()
self.disk0.childImage(mdesc.disks()[0])
self.disk0.pio = self.iobus.master
self.disk0.pio = self.iobus.mem_side_ports
# The puart0 and hvuart are placed on the IO bus, so create ranges
# for them. The remaining IO range is rather fragmented, so poke
@@ -160,12 +160,12 @@ def makeSparcSystem(mem_mode, mdesc=None, cmdline=None):
self.partition_desc = SimpleMemory(image_file=binary('1up-md.bin'),
range=AddrRange(0x1f12000000, size='8kB'))
self.rom.port = self.membus.master
self.nvram.port = self.membus.master
self.hypervisor_desc.port = self.membus.master
self.partition_desc.port = self.membus.master
self.rom.port = self.membus.mem_side_ports
self.nvram.port = self.membus.mem_side_ports
self.hypervisor_desc.port = self.membus.mem_side_ports
self.partition_desc.port = self.membus.mem_side_ports
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
self.workload = workload
@@ -189,10 +189,10 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
self.iobus = IOXBar()
if not ruby:
self.bridge = Bridge(delay='50ns')
self.bridge.master = self.iobus.slave
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.membus = MemBus()
self.membus.badaddr_responder.warn_access = "warn"
self.bridge.slave = self.membus.master
self.bridge.cpu_side_port = self.membus.mem_side_ports
self.mem_mode = mem_mode
@@ -299,13 +299,13 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
# I/O traffic enters iobus
self.external_io = ExternalMaster(port_data="external_io",
port_type=external_memory)
self.external_io.port = self.iobus.slave
self.external_io.port = self.iobus.cpu_side_ports
# Ensure iocache only receives traffic destined for (actual) memory.
self.iocache = ExternalSlave(port_data="iocache",
port_type=external_memory,
addr_ranges=self.mem_ranges)
self.iocache.port = self.iobus.master
self.iocache.port = self.iobus.mem_side_ports
# Let system_port get to nvmem and nothing else.
self.bridge.ranges = [self.realview.nvmem.range]
@@ -336,7 +336,7 @@ def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
attach_9p(self.realview, self.iobus)
if not ruby:
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
if ruby:
if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1:
@@ -362,15 +362,15 @@ def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.mem_ranges = [AddrRange('1GB')]
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = self.membus.mem_side_ports
self.disks = makeCowDisks(mdesc.disks())
self.malta = BaseMalta()
self.malta.attachIO(self.iobus)
self.malta.ide.pio = self.iobus.master
self.malta.ide.dma = self.iobus.slave
self.malta.ethernet.pio = self.iobus.master
self.malta.ethernet.dma = self.iobus.slave
self.malta.ide.pio = self.iobus.mem_side_ports
self.malta.ide.dma = self.iobus.cpu_side_ports
self.malta.ethernet.pio = self.iobus.mem_side_ports
self.malta.ethernet.dma = self.iobus.cpu_side_ports
self.simple_disk = SimpleDisk(disk=RawDiskImage(
image_file = mdesc.disks()[0], read_only = True))
self.mem_mode = mem_mode
@@ -380,7 +380,7 @@ def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
cmdline = 'root=/dev/hda1 console=ttyS0'
self.workload = KernelWorkload(command_line=fillInCmdline(mdesc, cmdline))
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
return self
@@ -400,8 +400,8 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# North Bridge
x86_sys.iobus = IOXBar()
x86_sys.bridge = Bridge(delay='50ns')
x86_sys.bridge.master = x86_sys.iobus.slave
x86_sys.bridge.slave = x86_sys.membus.master
x86_sys.bridge.mem_side_port = x86_sys.iobus.cpu_side_ports
x86_sys.bridge.cpu_side_port = x86_sys.membus.mem_side_ports
# Allow the bridge to pass through:
# 1) kernel configured PCI device memory map address: address range
# [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
@@ -420,8 +420,8 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# Create a bridge from the IO bus to the memory bus to allow access to
# the local APIC (two pages)
x86_sys.apicbridge = Bridge(delay='50ns')
x86_sys.apicbridge.slave = x86_sys.iobus.master
x86_sys.apicbridge.master = x86_sys.membus.slave
x86_sys.apicbridge.cpu_side_port = x86_sys.iobus.mem_side_ports
x86_sys.apicbridge.mem_side_port = x86_sys.membus.cpu_side_ports
x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
interrupts_address_space_base +
numCPUs * APIC_range_size
@@ -430,7 +430,7 @@ def connectX86ClassicSystem(x86_sys, numCPUs):
# connect the io bus
x86_sys.pc.attachIO(x86_sys.iobus)
x86_sys.system_port = x86_sys.membus.slave
x86_sys.system_port = x86_sys.membus.cpu_side_ports
def connectX86RubySystem(x86_sys):
# North Bridge
@@ -646,13 +646,13 @@ def makeBareMetalRiscvSystem(mem_mode, mdesc=None, cmdline=None):
self.membus = MemBus()
self.bridge = Bridge(delay='50ns')
self.bridge.master = self.iobus.slave
self.bridge.slave = self.membus.master
self.bridge.mem_side_port = self.iobus.cpu_side_ports
self.bridge.cpu_side_port = self.membus.mem_side_ports
# Sv39 has 56 bit physical addresses; use the upper 8 bit for the IO space
IO_address_space_base = 0x00FF000000000000
self.bridge.ranges = [AddrRange(IO_address_space_base, Addr.max)]
self.system_port = self.membus.slave
self.system_port = self.membus.cpu_side_ports
return self
def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):

8
configs/common/GPUTLBConfig.py
View File

@@ -136,7 +136,7 @@ def config_tlb_hierarchy(options, system, shader_idx):
#===========================================================
# Specify the TLB hierarchy (i.e., port connections)
# All TLBs but the last level TLB need to have a memSidePort (master)
# All TLBs but the last level TLB need to have a memSidePort
#===========================================================
# Each TLB is connected with its Coalescer through a single port.
@@ -152,7 +152,7 @@ def config_tlb_hierarchy(options, system, shader_idx):
system.%s_tlb[%d].cpu_side_ports[0]' % \
(name, index, name, index))
# Connect the cpuSidePort (slave) of all the coalescers in level 1
# Connect the cpuSidePort of all the coalescers in level 1
# < Modify here if you want a different configuration >
for TLB_type in L1:
name = TLB_type['name']
@@ -188,8 +188,8 @@ def config_tlb_hierarchy(options, system, shader_idx):
(shader_idx, index, scalar_tlb_index,
scalar_tlb_port_id))
# Connect the memSidePorts (masters) of all the TLBs with the
# cpuSidePorts (slaves) of the Coalescers of the next level
# Connect the memSidePorts of all the TLBs with the
# cpuSidePorts of the Coalescers of the next level
# < Modify here if you want a different configuration >
# L1 <-> L2
l2_coalescer_index = 0

76
configs/common/HMC.py
View File

@@ -356,25 +356,25 @@ def config_hmc_host_ctrl(opt, system):
mb = system.membus
for i in range(opt.num_links_controllers):
if opt.enable_global_monitor:
mb.master = hh.lmonitor[i].slave
hh.lmonitor[i].master = hh.seriallink[i].slave
mb.mem_side_ports = hh.lmonitor[i].cpu_side_port
hh.lmonitor[i].mem_side_port = hh.seriallink[i].cpu_side_port
else:
mb.master = hh.seriallink[i].slave
mb.mem_side_ports = hh.seriallink[i].cpu_side_port
if opt.arch == "mixed":
mb = system.membus
if opt.enable_global_monitor:
mb.master = hh.lmonitor[0].slave
hh.lmonitor[0].master = hh.seriallink[0].slave
mb.master = hh.lmonitor[1].slave
hh.lmonitor[1].master = hh.seriallink[1].slave
mb.mem_side_ports = hh.lmonitor[0].cpu_side_port
hh.lmonitor[0].mem_side_port = hh.seriallink[0].cpu_side_port
mb.mem_side_ports = hh.lmonitor[1].cpu_side_port
hh.lmonitor[1].mem_side_port = hh.seriallink[1].cpu_side_port
else:
mb.master = hh.seriallink[0].slave
mb.master = hh.seriallink[1].slave
mb.mem_side_ports = hh.seriallink[0].cpu_side_port
mb.mem_side_ports = hh.seriallink[1].cpu_side_port
if opt.arch == "same":
for i in range(opt.num_links_controllers):
if opt.enable_global_monitor:
hh.lmonitor[i].master = hh.seriallink[i].slave
hh.lmonitor[i].mem_side_port = hh.seriallink[i].cpu_side_port
return system
@@ -412,11 +412,13 @@ def config_hmc_dev(opt, system, hmc_host):
# Attach 4 serial link to 4 crossbar/s
for i in range(opt.num_serial_links):
if opt.enable_link_monitor:
system.hmc_host.seriallink[i].master = \
system.hmc_dev.lmonitor[i].slave
system.hmc_dev.lmonitor[i].master = system.hmc_dev.xbar[i].slave
system.hmc_host.seriallink[i].mem_side_port = \
system.hmc_dev.lmonitor[i].cpu_side_port
system.hmc_dev.lmonitor[i].mem_side_port = \
system.hmc_dev.xbar[i].cpu_side_ports
else:
system.hmc_host.seriallink[i].master = system.hmc_dev.xbar[i].slave
system.hmc_host.seriallink[i].mem_side_port = \
system.hmc_dev.xbar[i].cpu_side_ports
# Connecting xbar with each other for request arriving at the wrong xbar,
# then it will be forward to correct xbar. Bridge is used to connect xbars
@@ -432,7 +434,7 @@ def config_hmc_dev(opt, system, hmc_host):
it = iter(list(range(len(system.hmc_dev.buffers))))
# necesarry to add system_port to one of the xbar
system.system_port = system.hmc_dev.xbar[3].slave
system.system_port = system.hmc_dev.xbar[3].cpu_side_ports
# iterate over all the crossbars and connect them as required
for i in range(numx):
@@ -448,10 +450,10 @@ def config_hmc_dev(opt, system, hmc_host):
(j + 1) * int(opt.mem_chunk)]
# Connect the bridge between corssbars
system.hmc_dev.xbar[i].master = system.hmc_dev.buffers[
index].slave
system.hmc_dev.buffers[
index].master = system.hmc_dev.xbar[j].slave
system.hmc_dev.xbar[i].mem_side_ports = \
system.hmc_dev.buffers[index].cpu_side_port
system.hmc_dev.buffers[index].mem_side_port = \
system.hmc_dev.xbar[j].cpu_side_ports
else:
# Don't connect the xbar to itself
pass
@@ -460,25 +462,37 @@ def config_hmc_dev(opt, system, hmc_host):
# can only direct traffic to it local vaults
if opt.arch == "mixed":
system.hmc_dev.buffer30 = Bridge(ranges=system.mem_ranges[0:4])
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer30.slave
system.hmc_dev.buffer30.master = system.hmc_dev.xbar[0].slave
system.hmc_dev.xbar[3].mem_side_ports = \
system.hmc_dev.buffer30.cpu_side_port
system.hmc_dev.buffer30.mem_side_port = \
system.hmc_dev.xbar[0].cpu_side_ports
system.hmc_dev.buffer31 = Bridge(ranges=system.mem_ranges[4:8])
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer31.slave
system.hmc_dev.buffer31.master = system.hmc_dev.xbar[1].slave
system.hmc_dev.xbar[3].mem_side_ports = \
system.hmc_dev.buffer31.cpu_side_port
system.hmc_dev.buffer31.mem_side_port = \
system.hmc_dev.xbar[1].cpu_side_ports
system.hmc_dev.buffer32 = Bridge(ranges=system.mem_ranges[8:12])
system.hmc_dev.xbar[3].master = system.hmc_dev.buffer32.slave
system.hmc_dev.buffer32.master = system.hmc_dev.xbar[2].slave
system.hmc_dev.xbar[3].mem_side_ports = \
system.hmc_dev.buffer32.cpu_side_port
system.hmc_dev.buffer32.mem_side_port = \
system.hmc_dev.xbar[2].cpu_side_ports
system.hmc_dev.buffer20 = Bridge(ranges=system.mem_ranges[0:4])
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer20.slave
system.hmc_dev.buffer20.master = system.hmc_dev.xbar[0].slave
system.hmc_dev.xbar[2].mem_side_ports = \
system.hmc_dev.buffer20.cpu_side_port
system.hmc_dev.buffer20.mem_side_port = \
system.hmc_dev.xbar[0].cpu_side_ports
system.hmc_dev.buffer21 = Bridge(ranges=system.mem_ranges[4:8])
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer21.slave
system.hmc_dev.buffer21.master = system.hmc_dev.xbar[1].slave
system.hmc_dev.xbar[2].mem_side_ports = \
system.hmc_dev.buffer21.cpu_side_port
system.hmc_dev.buffer21.mem_side_port = \
system.hmc_dev.xbar[1].cpu_side_ports
system.hmc_dev.buffer23 = Bridge(ranges=system.mem_ranges[12:16])
system.hmc_dev.xbar[2].master = system.hmc_dev.buffer23.slave
system.hmc_dev.buffer23.master = system.hmc_dev.xbar[3].slave
system.hmc_dev.xbar[2].mem_side_ports = \
system.hmc_dev.buffer23.cpu_side_port
system.hmc_dev.buffer23.mem_side_port = \
system.hmc_dev.xbar[3].cpu_side_ports

2
configs/common/MemConfig.py
View File

@@ -156,7 +156,7 @@ def config_mem(options, system):
if opt_external_memory_system:
subsystem.external_memory = m5.objects.ExternalSlave(
port_type=opt_external_memory_system,
port_data="init_mem0", port=xbar.master,
port_data="init_mem0", port=xbar.mem_side_ports,
addr_ranges=system.mem_ranges)
subsystem.workload.addr_check = False
return