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arch-vega: Add support for S_ICACHE_INV instruction

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Previously, the S_ICACHE_INV instruction was unimplemented and
simulation panicked if it was encountered. This commit adds support for
executing the instruction by injecting a memory barrier in the scalar
pipeline and invalidating the ICACHE (or SQC)

Change-Id: I0fbd4e53f630a267971a23cea6f17d4fef403d15
This commit is contained in:
Vishnu Ramadas
2024-02-09 12:19:08 -06:00
parent 85680ea58e
commit 8054459df6
1 changed files with 23 additions and 1 deletions
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24
src/arch/amdgpu/vega/insts/sopp.cc
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@@ -669,6 +669,9 @@ namespace VegaISA
Inst_SOPP__S_ICACHE_INV::Inst_SOPP__S_ICACHE_INV(InFmt_SOPP *iFmt)
: Inst_SOPP(iFmt, "s_icache_inv")
{
setFlag(MemBarrier);
setFlag(GPUStaticInst::MemSync);
setFlag(MemSync);
} // Inst_SOPP__S_ICACHE_INV
Inst_SOPP__S_ICACHE_INV::~Inst_SOPP__S_ICACHE_INV()
@@ -683,7 +686,26 @@ namespace VegaISA
void
Inst_SOPP__S_ICACHE_INV::execute(GPUDynInstPtr gpuDynInst)
{
panicUnimplemented();
Wavefront *wf = gpuDynInst->wavefront();
if (gpuDynInst->exec_mask.none()) {
wf->decLGKMInstsIssued();
return;
}
gpuDynInst->execUnitId = wf->execUnitId;
gpuDynInst->latency.init(gpuDynInst->computeUnit());
gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod());
gpuDynInst->resetEntireStatusVector();
gpuDynInst->setStatusVector(0, 1);
RequestPtr req = std::make_shared<Request>(0, 0, 0,
gpuDynInst->computeUnit()->
requestorId(), 0,
gpuDynInst->wfDynId);
gpuDynInst->setRequestFlags(req);
gpuDynInst->computeUnit()->scalarMemoryPipe.
injectScalarMemFence(gpuDynInst, false, req);
} // execute
// --- Inst_SOPP__S_INCPERFLEVEL class methods ---