From 8054459df6583f42740a5a2fa5f978d5b0207530 Mon Sep 17 00:00:00 2001 From: Vishnu Ramadas Date: Fri, 9 Feb 2024 12:19:08 -0600 Subject: [PATCH] arch-vega: Add support for S_ICACHE_INV instruction Previously, the S_ICACHE_INV instruction was unimplemented and simulation panicked if it was encountered. This commit adds support for executing the instruction by injecting a memory barrier in the scalar pipeline and invalidating the ICACHE (or SQC) Change-Id: I0fbd4e53f630a267971a23cea6f17d4fef403d15 --- src/arch/amdgpu/vega/insts/sopp.cc | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/arch/amdgpu/vega/insts/sopp.cc b/src/arch/amdgpu/vega/insts/sopp.cc index df5cdbf681..781113b204 100644 --- a/src/arch/amdgpu/vega/insts/sopp.cc +++ b/src/arch/amdgpu/vega/insts/sopp.cc @@ -669,6 +669,9 @@ namespace VegaISA Inst_SOPP__S_ICACHE_INV::Inst_SOPP__S_ICACHE_INV(InFmt_SOPP *iFmt) : Inst_SOPP(iFmt, "s_icache_inv") { + setFlag(MemBarrier); + setFlag(GPUStaticInst::MemSync); + setFlag(MemSync); } // Inst_SOPP__S_ICACHE_INV Inst_SOPP__S_ICACHE_INV::~Inst_SOPP__S_ICACHE_INV() @@ -683,7 +686,26 @@ namespace VegaISA void Inst_SOPP__S_ICACHE_INV::execute(GPUDynInstPtr gpuDynInst) { - panicUnimplemented(); + Wavefront *wf = gpuDynInst->wavefront(); + + if (gpuDynInst->exec_mask.none()) { + wf->decLGKMInstsIssued(); + return; + } + + gpuDynInst->execUnitId = wf->execUnitId; + gpuDynInst->latency.init(gpuDynInst->computeUnit()); + gpuDynInst->latency.set(gpuDynInst->computeUnit()->clockPeriod()); + + gpuDynInst->resetEntireStatusVector(); + gpuDynInst->setStatusVector(0, 1); + RequestPtr req = std::make_shared(0, 0, 0, + gpuDynInst->computeUnit()-> + requestorId(), 0, + gpuDynInst->wfDynId); + gpuDynInst->setRequestFlags(req); + gpuDynInst->computeUnit()->scalarMemoryPipe. + injectScalarMemFence(gpuDynInst, false, req); } // execute // --- Inst_SOPP__S_INCPERFLEVEL class methods ---