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arch-riscv: Correct interrupt order

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In Section 3.1.14 of Volume II Riscv Spec., the interrupt order
should be MEI, MSI, MTI, SEI, SSI, STI and so on.

issues:
https://gem5.atlassian.net/browse/GEM5-889

Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67211
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Roger Chang
2023-01-03 14:00:32 +08:00
parent 3f2c55cb63
commit 7c670c1667
1 changed files with 3 additions and 3 deletions
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6
src/arch/riscv/interrupts.hh
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@@ -125,9 +125,9 @@ class Interrupts : public BaseInterrupts
return std::make_shared<NonMaskableInterruptFault>();
std::bitset<NumInterruptTypes> mask = globalMask();
const std::vector<int> interrupt_order {
INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE,
INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER,
INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER
INT_EXT_MACHINE, INT_SOFTWARE_MACHINE, INT_TIMER_MACHINE,
INT_EXT_SUPER, INT_SOFTWARE_SUPER, INT_TIMER_SUPER,
INT_EXT_USER, INT_SOFTWARE_USER, INT_TIMER_USER
};
for (const int &id : interrupt_order)
if (checkInterrupt(id) && mask[id])