From 7c670c16675cd0fa155d04c8966b9b02ca53593d Mon Sep 17 00:00:00 2001 From: Roger Chang Date: Tue, 3 Jan 2023 14:00:32 +0800 Subject: [PATCH] arch-riscv: Correct interrupt order In Section 3.1.14 of Volume II Riscv Spec., the interrupt order should be MEI, MSI, MTI, SEI, SSI, STI and so on. issues: https://gem5.atlassian.net/browse/GEM5-889 Change-Id: I357c86eecd74e9e65bbfd3d4d31e68bc276f8760 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/67211 Maintainer: Jason Lowe-Power Reviewed-by: Yu-hsin Wang Tested-by: kokoro Reviewed-by: Jui-min Lee Reviewed-by: Jason Lowe-Power --- src/arch/riscv/interrupts.hh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/riscv/interrupts.hh b/src/arch/riscv/interrupts.hh index f10c5f386a..a1ee396cd4 100644 --- a/src/arch/riscv/interrupts.hh +++ b/src/arch/riscv/interrupts.hh @@ -125,9 +125,9 @@ class Interrupts : public BaseInterrupts return std::make_shared(); std::bitset mask = globalMask(); const std::vector interrupt_order { - INT_EXT_MACHINE, INT_TIMER_MACHINE, INT_SOFTWARE_MACHINE, - INT_EXT_SUPER, INT_TIMER_SUPER, INT_SOFTWARE_SUPER, - INT_EXT_USER, INT_TIMER_USER, INT_SOFTWARE_USER + INT_EXT_MACHINE, INT_SOFTWARE_MACHINE, INT_TIMER_MACHINE, + INT_EXT_SUPER, INT_SOFTWARE_SUPER, INT_TIMER_SUPER, + INT_EXT_USER, INT_SOFTWARE_USER, INT_TIMER_USER }; for (const int &id : interrupt_order) if (checkInterrupt(id) && mask[id])