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arch-riscv: Fix vsadd_vi and vsaddu_vi to match v-spec (#805)

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This commit fixes the implementation of two instructions, vsadd_vi and
vsaddu_vi, in the OPIVI category
to match the RISC-V vector specification.

According to
[riscv-v-spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#101-vector-arithmetic-instruction-encoding),
the immediate field of these two instructions should be sign extended.

> For integer operations, the scalar can be a 5-bit immediate, imm[4:0],
encoded in the rs1 field. The value is sign-extended to SEW bits, unless
otherwise specified.

There is an example in both
[vsadd](https://github.com/QQeg/rvv_intrinsic_testcases/tree/master/vsadd_vi)
and
[vsaddu](https://github.com/QQeg/rvv_intrinsic_testcases/tree/master/vsaddu_vi).

Change-Id: Ib877627ba01c0868b2103d41613651df488fca13
This commit is contained in:
QQeg
2024-01-25 09:21:26 +08:00
committed by GitHub
parent 6dd936e5b5
commit 7a96709b11
1 changed files with 2 additions and 2 deletions
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4
src/arch/riscv/isa/decoder.isa
View File

@@ -3467,11 +3467,11 @@ decode QUADRANT default Unknown::unknown() {
}
format VectorIntVxsatFormat{
0x20: vsaddu_vi({{
Vd_vu[i] = sat_addu<vu>(Vs2_vu[i], (vu)SIMM5,
Vd_vu[i] = sat_addu<vu>(Vs2_vu[i], (vu)sext<5>(SIMM5),
vxsatptr);
}}, OPIVI, VectorIntegerArithOp);
0x21: vsadd_vi({{
Vd_vu[i] = sat_add<vi>(Vs2_vu[i], (vu)SIMM5,
Vd_vi[i] = sat_add<vi>(Vs2_vi[i], (vi)sext<5>(SIMM5),
vxsatptr);
}}, OPIVI, VectorIntegerArithOp);
}