From 7a96709b1141aecbb7e502435cdacc2204e56622 Mon Sep 17 00:00:00 2001 From: QQeg <78740113+QQeg@users.noreply.github.com> Date: Thu, 25 Jan 2024 09:21:26 +0800 Subject: [PATCH] arch-riscv: Fix vsadd_vi and vsaddu_vi to match v-spec (#805) This commit fixes the implementation of two instructions, vsadd_vi and vsaddu_vi, in the OPIVI category to match the RISC-V vector specification. According to [riscv-v-spec](https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#101-vector-arithmetic-instruction-encoding), the immediate field of these two instructions should be sign extended. > For integer operations, the scalar can be a 5-bit immediate, imm[4:0], encoded in the rs1 field. The value is sign-extended to SEW bits, unless otherwise specified. There is an example in both [vsadd](https://github.com/QQeg/rvv_intrinsic_testcases/tree/master/vsadd_vi) and [vsaddu](https://github.com/QQeg/rvv_intrinsic_testcases/tree/master/vsaddu_vi). Change-Id: Ib877627ba01c0868b2103d41613651df488fca13 --- src/arch/riscv/isa/decoder.isa | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 2f2d43f0cf..678e662251 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -3467,11 +3467,11 @@ decode QUADRANT default Unknown::unknown() { } format VectorIntVxsatFormat{ 0x20: vsaddu_vi({{ - Vd_vu[i] = sat_addu(Vs2_vu[i], (vu)SIMM5, + Vd_vu[i] = sat_addu(Vs2_vu[i], (vu)sext<5>(SIMM5), vxsatptr); }}, OPIVI, VectorIntegerArithOp); 0x21: vsadd_vi({{ - Vd_vu[i] = sat_add(Vs2_vu[i], (vu)SIMM5, + Vd_vi[i] = sat_add(Vs2_vi[i], (vi)sext<5>(SIMM5), vxsatptr); }}, OPIVI, VectorIntegerArithOp); }