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arch-arm: Fix cache line size for cache maintenace inst

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Cache maintenance operations operate on whole cache blocks. This
changeset uses the system cache line size as the size of the cache
maintenance requests and masks the lower bits of the effective
address.

Change-Id: I6e7aefff51670c8cac39e4e73db21a0c5a0b7aef
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7824
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Nikos Nikoleris
2017-12-19 21:43:51 +00:00
parent f4e27c3ff5
commit 760e2eb6f4
1 changed files with 7 additions and 7 deletions
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14
src/arch/arm/isa/templates/misc.isa
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@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2010-2013,2017 ARM Limited
// Copyright (c) 2010-2013,2017-2018 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -646,9 +646,9 @@ def template Mcr15Execute {{
}
if (fault == NoFault) {
Addr size = 64;
EA &= ~(size - 1);
fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL);
Addr op_size = xc->tcBase()->getSystemPtr()->cacheLineSize();
EA &= ~(op_size - 1);
fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL);
}
} else {
xc->setPredicate(false);
@@ -675,9 +675,9 @@ def template Mcr15InitiateAcc {{
}
if (fault == NoFault) {
Addr size = 64;
EA &= ~(size - 1);
fault = xc->writeMem(NULL, size, EA, memAccessFlags, NULL);
Addr op_size = xc->tcBase()->getSystemPtr()->cacheLineSize();
EA &= ~(op_size - 1);
fault = xc->writeMem(NULL, op_size, EA, memAccessFlags, NULL);
}
} else {
xc->setPredicate(false);