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arch-arm: Fault when dc ivac is executed from EL0

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A previous change enabled execution of dc ivac from EL0 when
SCTLR_EL1.UCI=1. The Arm ARM specifies that dc ivac is the only data
cache maintenance operation by VA that cannot be executed from
EL0. This changeset essential reverts the change:
8d43922 arch-arm: Allow dc ivac from EL0 when SCTLR_EL1.UCI=1

Change-Id: Ia25fab13846a151f548e649a16067feb1ff65c9c
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7823
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Nikos Nikoleris
2017-12-19 16:58:33 +00:00
parent b72d69c5ca
commit f4e27c3ff5
1 changed files with 2 additions and 3 deletions
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5
src/arch/arm/miscregs.cc
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@@ -922,8 +922,7 @@ canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc)
if (el == EL0 && !sctlr.dze)
return false;
}
if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt ||
reg == MISCREG_DC_IVAC_Xt) {
if (reg == MISCREG_DC_CVAC_Xt || reg == MISCREG_DC_CIVAC_Xt) {
SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR_EL1);
if (el == EL0 && !sctlr.uci)
return false;
@@ -3557,7 +3556,7 @@ ISA::initializeMiscRegMetadata()
.writes(1).exceptUserMode();
InitReg(MISCREG_DC_IVAC_Xt)
.warnNotFail()
.writes(1);
.writes(1).exceptUserMode();
InitReg(MISCREG_DC_ISW_Xt)
.warnNotFail()
.writes(1).exceptUserMode();