arch-riscv: Fix c.fsw source register (#1005)

RISC-V C.FSW format:


![image](https://github.com/gem5/gem5/assets/32214817/31f46525-23e1-4b36-91ee-968f18b9d32a)
Source register is bit 2-4, not bit 20-24
 

ee6f1377d7/src/arch/riscv/isa/bitfields.isa (L112)


ee6f1377d7/src/arch/riscv/isa/operands.isa (L88)


ee6f1377d7/src/arch/riscv/isa/bitfields.isa (L87)


ee6f1377d7/src/arch/riscv/isa/operands.isa (L80)

src/arch/riscv/isa/decoder.isa

@@ -183,7 +183,7 @@ decode QUADRANT default Unknown::unknown() {
                         return std::make_shared<IllegalInstFault>("FPU is off",
                                                                    machInst);
 
-                    Mem_uw = unboxF32(boxF32(Fs2_bits));
+                    Mem_uw = unboxF32(boxF32(Fp2_bits));
                 }}, {{
                     EA = (uint32_t)(Rp1_uw + offset);
                 }});