From 71b0b1f2b68f5d4245f132ebe05ce9484a9875b1 Mon Sep 17 00:00:00 2001 From: Yu-Cheng Chang Date: Mon, 8 Apr 2024 23:30:54 +0800 Subject: [PATCH] arch-riscv: Fix c.fsw source register (#1005) RISC-V C.FSW format: ![image](https://github.com/gem5/gem5/assets/32214817/31f46525-23e1-4b36-91ee-968f18b9d32a) Source register is bit 2-4, not bit 20-24 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/bitfields.isa#L112 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/operands.isa#L88 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/bitfields.isa#L87 https://github.com/gem5/gem5/blob/ee6f1377d7c54422137dfa47cd4d73407814867d/src/arch/riscv/isa/operands.isa#L80 --- src/arch/riscv/isa/decoder.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa index 995b4936b5..d632f722fc 100644 --- a/src/arch/riscv/isa/decoder.isa +++ b/src/arch/riscv/isa/decoder.isa @@ -183,7 +183,7 @@ decode QUADRANT default Unknown::unknown() { return std::make_shared("FPU is off", machInst); - Mem_uw = unboxF32(boxF32(Fs2_bits)); + Mem_uw = unboxF32(boxF32(Fp2_bits)); }}, {{ EA = (uint32_t)(Rp1_uw + offset); }});