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arch-arm: Remove unused TLBType

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The cached state is global now (per-MMU)

Change-Id: I70bc847813086f678b4ff32722b7f6e3ceaae6f5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50527
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-09-17 13:41:05 +01:00
parent 377155c10b
commit 6b2faf3723
3 changed files with 4 additions and 14 deletions
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7
src/arch/arm/isa.cc
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@@ -905,10 +905,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
CPSR old_cpsr = miscRegs[MISCREG_CPSR];
int old_mode = old_cpsr.mode;
CPSR cpsr = val;
if (cpsr.pan != old_cpsr.pan) {
getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
}
if (cpsr.il != old_cpsr.il) {
if (cpsr.pan != old_cpsr.pan || cpsr.il != old_cpsr.il) {
getMMUPtr(tc)->invalidateMiscReg();
}
@@ -2271,7 +2268,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
case MISCREG_PAN:
{
// PAN is affecting data accesses
getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
getMMUPtr(tc)->invalidateMiscReg();
CPSR cpsr = miscRegs[MISCREG_CPSR];
cpsr.pan = (uint8_t) ((CPSR) newVal).pan;

2
src/arch/arm/mmu.cc
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@@ -160,7 +160,7 @@ MMU::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
}
void
MMU::invalidateMiscReg(TLBType type)
MMU::invalidateMiscReg()
{
s1State.miscRegValid = false;
}

9
src/arch/arm/mmu.hh
View File

@@ -117,13 +117,6 @@ class MMU : public BaseMMU
S12E1Tran = 0x100
};
enum TLBType
{
I_TLBS = 0x01,
D_TLBS = 0x10,
ALL_TLBS = 0x11
};
struct CachedState {
explicit CachedState(MMU *_mmu, bool stage2)
: mmu(_mmu), isStage2(stage2)
@@ -250,7 +243,7 @@ class MMU : public BaseMMU
void takeOverFrom(BaseMMU *old_mmu) override;
void invalidateMiscReg(TLBType type = ALL_TLBS);
void invalidateMiscReg();
template <typename OP>
void