diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8d5addcd15..9439d0eba5 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -905,10 +905,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
         CPSR old_cpsr = miscRegs[MISCREG_CPSR];
         int old_mode = old_cpsr.mode;
         CPSR cpsr = val;
-        if (cpsr.pan != old_cpsr.pan) {
-            getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
-        }
-        if (cpsr.il != old_cpsr.il) {
+        if (cpsr.pan != old_cpsr.pan || cpsr.il != old_cpsr.il) {
             getMMUPtr(tc)->invalidateMiscReg();
         }
 
@@ -2271,7 +2268,7 @@ ISA::setMiscReg(int misc_reg, RegVal val)
           case MISCREG_PAN:
             {
                 // PAN is affecting data accesses
-                getMMUPtr(tc)->invalidateMiscReg(MMU::D_TLBS);
+                getMMUPtr(tc)->invalidateMiscReg();
 
                 CPSR cpsr = miscRegs[MISCREG_CPSR];
                 cpsr.pan = (uint8_t) ((CPSR) newVal).pan;
diff --git a/src/arch/arm/mmu.cc b/src/arch/arm/mmu.cc
index d2fc706e2c..5f0b64eb9a 100644
--- a/src/arch/arm/mmu.cc
+++ b/src/arch/arm/mmu.cc
@@ -160,7 +160,7 @@ MMU::translateFunctional(ThreadContext *tc, Addr va, Addr &pa)
 }
 
 void
-MMU::invalidateMiscReg(TLBType type)
+MMU::invalidateMiscReg()
 {
     s1State.miscRegValid = false;
 }
diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh
index 0e1fd87e76..f6ebd89141 100644
--- a/src/arch/arm/mmu.hh
+++ b/src/arch/arm/mmu.hh
@@ -117,13 +117,6 @@ class MMU : public BaseMMU
         S12E1Tran = 0x100
     };
 
-    enum TLBType
-    {
-        I_TLBS = 0x01,
-        D_TLBS = 0x10,
-        ALL_TLBS = 0x11
-    };
-
     struct CachedState {
         explicit CachedState(MMU *_mmu, bool stage2)
           : mmu(_mmu), isStage2(stage2)
@@ -250,7 +243,7 @@ class MMU : public BaseMMU
 
     void takeOverFrom(BaseMMU *old_mmu) override;
 
-    void invalidateMiscReg(TLBType type = ALL_TLBS);
+    void invalidateMiscReg();
 
     template <typename OP>
     void