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arch-arm: TLBIs targeting EL2 regime are executable from S state

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Those AArch64 instructions/registers were labelled as executable
from EL3 only if SCR_EL3.NS == 1. This is not valid anymore
after the introduction of FEAT_SEL2

Change-Id: Ie7b56f3fe779c3a99d4f0ef937c7c8ec0530b00e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-01-24 12:08:03 +00:00
parent 10dbfb8bb7
commit 6995a99d77
1 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/arch/arm/regs/misc.cc
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@@ -5352,13 +5352,13 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TLBI_IPAS2LE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2OS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2OS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2OS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1OS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2E1IS)
@@ -5366,13 +5366,13 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TLBI_IPAS2LE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2IS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2IS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2IS)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1IS)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_IPAS2E1)
@@ -5380,13 +5380,13 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TLBI_IPAS2LE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE2)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VAE2)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_ALLE1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_VALE2)
.monNonSecureWrite().hypWrite();
.monWrite().hypWrite();
InitReg(MISCREG_TLBI_VMALLS12E1)
.hypWrite().monSecureWrite().monNonSecureWrite();
InitReg(MISCREG_TLBI_ALLE3OS)