From 6995a99d776287390659ced0375ae315772d9aff Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Wed, 24 Jan 2024 12:08:03 +0000 Subject: [PATCH] arch-arm: TLBIs targeting EL2 regime are executable from S state Those AArch64 instructions/registers were labelled as executable from EL3 only if SCR_EL3.NS == 1. This is not valid anymore after the introduction of FEAT_SEL2 Change-Id: Ie7b56f3fe779c3a99d4f0ef937c7c8ec0530b00e Signed-off-by: Giacomo Travaglini --- src/arch/arm/regs/misc.cc | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index d29a8bc367..380db488ef 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -5352,13 +5352,13 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBI_IPAS2LE1OS) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_ALLE2OS) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_VAE2OS) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_ALLE1OS) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_VALE2OS) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_VMALLS12E1OS) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_IPAS2E1IS) @@ -5366,13 +5366,13 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBI_IPAS2LE1IS) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_ALLE2IS) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_VAE2IS) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_ALLE1IS) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_VALE2IS) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_VMALLS12E1IS) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_IPAS2E1) @@ -5380,13 +5380,13 @@ ISA::initializeMiscRegMetadata() InitReg(MISCREG_TLBI_IPAS2LE1) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_ALLE2) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_VAE2) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_ALLE1) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_VALE2) - .monNonSecureWrite().hypWrite(); + .monWrite().hypWrite(); InitReg(MISCREG_TLBI_VMALLS12E1) .hypWrite().monSecureWrite().monNonSecureWrite(); InitReg(MISCREG_TLBI_ALLE3OS)