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misc: Merge branch 'release-staging-v20.1.0.0' into develop

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Change-Id: I656a2d9512b1822a7e8d82606da7a0a5504d6820
This commit is contained in:
Bobby R. Bruce
2020-09-24 22:28:11 -07:00
parent d872fe2f17 bcc797a2cb
commit 63e9699256
4 changed files with 41 additions and 27 deletions
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26
src/arch/arm/fastmodel/CortexA76/thread_context.cc
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@@ -47,11 +47,11 @@ CortexA76TC::translateAddress(Addr &paddr, Addr vaddr)
{
// Determine what memory spaces are currently active.
Iris::CanonicalMsn in_msn;
switch (currEL(this)) {
case EL3:
switch (ArmISA::currEL(this)) {
case ArmISA::EL3:
in_msn = Iris::SecureMonitorMsn;
break;
case EL2:
case ArmISA::EL2:
in_msn = Iris::NsHypMsn;
break;
default:
@@ -59,7 +59,7 @@ CortexA76TC::translateAddress(Addr &paddr, Addr vaddr)
break;
}
Iris::CanonicalMsn out_msn = isSecure(this) ?
Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ?
Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn;
// Figure out what memory spaces match the canonical numbers we need.
@@ -108,7 +108,7 @@ CortexA76TC::readIntRegFlat(RegIndex idx) const
if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
ArmISA::CPSR new_cpsr = orig_cpsr;
new_cpsr.mode = MODE_MON;
new_cpsr.mode = ArmISA::MODE_MON;
non_const_this->setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr);
}
@@ -129,7 +129,7 @@ CortexA76TC::setIntRegFlat(RegIndex idx, RegVal val)
if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
ArmISA::CPSR new_cpsr = orig_cpsr;
new_cpsr.mode = MODE_MON;
new_cpsr.mode = ArmISA::MODE_MON;
setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr);
}
@@ -146,7 +146,7 @@ CortexA76TC::readCCRegFlat(RegIndex idx) const
RegVal result = Iris::ThreadContext::readCCRegFlat(idx);
switch (idx) {
case ArmISA::CCREG_NZ:
result = ((CPSR)result).nz;
result = ((ArmISA::CPSR)result).nz;
break;
case ArmISA::CCREG_FP:
result = bits(result, 31, 28);
@@ -163,14 +163,14 @@ CortexA76TC::setCCRegFlat(RegIndex idx, RegVal val)
switch (idx) {
case ArmISA::CCREG_NZ:
{
CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
cpsr.nz = val;
val = cpsr;
}
break;
case ArmISA::CCREG_FP:
{
FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR);
ArmISA::FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR);
val = insertBits(fpscr, 31, 28, val);
}
break;
@@ -921,10 +921,10 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::flattenedIntIdxNameMap({
{ ArmISA::INTREG_R13_FIQ, "X29" },
{ ArmISA::INTREG_R14_FIQ, "X30" },
// Skip zero, ureg0-2, and dummy regs.
{ INTREG_SP0, "SP_EL0" },
{ INTREG_SP1, "SP_EL1" },
{ INTREG_SP2, "SP_EL2" },
{ INTREG_SP3, "SP_EL3" },
{ ArmISA::INTREG_SP0, "SP_EL0" },
{ ArmISA::INTREG_SP1, "SP_EL1" },
{ ArmISA::INTREG_SP2, "SP_EL2" },
{ ArmISA::INTREG_SP3, "SP_EL3" },
});
Iris::ThreadContext::IdxNameMap CortexA76TC::ccRegIdxNameMap({

14
src/arch/arm/fastmodel/iris/interrupts.cc
View File

@@ -28,7 +28,7 @@
#include "arch/arm/fastmodel/iris/interrupts.hh"
#include "arch/arm/fastmodel/iris/thread_context.hh"
#include "arch/arm/isa_traits.hh"
#include "arch/arm/interrupts.hh"
#include "arch/arm/miscregs.hh"
#include "arch/arm/miscregs_types.hh"
#include "arch/arm/types.hh"
@@ -86,12 +86,12 @@ Iris::Interrupts::serialize(CheckpointOut &cp) const
for (bool &i: interrupts)
i = false;
interrupts[INT_ABT] = phys_abort;
interrupts[INT_IRQ] = phys_irq;
interrupts[INT_FIQ] = phys_fiq;
interrupts[INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX);
interrupts[INT_VIRT_IRQ] = virt_irq;
interrupts[INT_VIRT_FIQ] = virt_fiq;
interrupts[ArmISA::INT_ABT] = phys_abort;
interrupts[ArmISA::INT_IRQ] = phys_irq;
interrupts[ArmISA::INT_FIQ] = phys_fiq;
interrupts[ArmISA::INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX);
interrupts[ArmISA::INT_VIRT_IRQ] = virt_irq;
interrupts[ArmISA::INT_VIRT_FIQ] = virt_fiq;
for (int i = 0; i < NumInterruptTypes; i++) {
if (interrupts[i])

24
src/arch/arm/fastmodel/iris/thread_context.hh
View File

@@ -445,12 +445,6 @@ class ThreadContext : public ::ThreadContext
panic("%s not implemented.", __FUNCTION__);
}
void
syscall() override
{
panic("%s not implemented.", __FUNCTION__);
}
/** @{ */
/**
* Flat register interfaces
@@ -517,6 +511,24 @@ class ThreadContext : public ::ThreadContext
void setCCRegFlat(RegIndex idx, RegVal val) override;
/** @} */
// hardware transactional memory
void
htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override
{
panic("%s not implemented.", __FUNCTION__);
}
BaseHTMCheckpointPtr &
getHtmCheckpointPtr() override
{
panic("%s not implemented.", __FUNCTION__);
}
void
setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) override
{
panic("%s not implemented.", __FUNCTION__);
}
};
} // namespace Iris

4
src/dev/arm/VExpressFastmodel.py
View File

@@ -24,6 +24,7 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.FastModelGIC import FastModelGIC, SCFastModelGIC
from m5.objects.Gic import ArmInterruptPin
from m5.objects.RealView import VExpress_GEM5_Base, HDLcd
class VExpressFastmodel(VExpress_GEM5_Base):
@@ -35,7 +36,8 @@ class VExpressFastmodel(VExpress_GEM5_Base):
))
hdlcd = HDLcd(
pxl_clk=VExpress_GEM5_Base.dcc.osc_pxl, pio_addr=0x2b000000, int_num=95)
pxl_clk=VExpress_GEM5_Base.dcc.osc_pxl, pio_addr=0x2b000000,
interrupt=ArmInterruptPin(num=95))
def __init__(self, *args, **kwargs):
super(VExpressFastmodel, self).__init__(*args, **kwargs)