From 281afe2be0c1ea4f9dfea96bbc0ca1265220bd7b Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 24 Sep 2020 00:34:54 -0700 Subject: [PATCH 1/3] fastmodel: Update for the isa_traits.hh changes. arch/arm/isa_traits.hh no longer has using namespace ArmISA, and also no longer directly or indirectly provides interrupt number related constants. Change-Id: Ieda31d1db4f85632a555b2f72ee8bff0aa159eee Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35037 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- .../arm/fastmodel/CortexA76/thread_context.cc | 26 +++++++++---------- src/arch/arm/fastmodel/iris/interrupts.cc | 14 +++++----- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc index 1259bf1662..238beec651 100644 --- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc +++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc @@ -47,11 +47,11 @@ CortexA76TC::translateAddress(Addr &paddr, Addr vaddr) { // Determine what memory spaces are currently active. Iris::CanonicalMsn in_msn; - switch (currEL(this)) { - case EL3: + switch (ArmISA::currEL(this)) { + case ArmISA::EL3: in_msn = Iris::SecureMonitorMsn; break; - case EL2: + case ArmISA::EL2: in_msn = Iris::NsHypMsn; break; default: @@ -59,7 +59,7 @@ CortexA76TC::translateAddress(Addr &paddr, Addr vaddr) break; } - Iris::CanonicalMsn out_msn = isSecure(this) ? + Iris::CanonicalMsn out_msn = ArmISA::isSecure(this) ? Iris::PhysicalMemorySecureMsn : Iris::PhysicalMemoryNonSecureMsn; // Figure out what memory spaces match the canonical numbers we need. @@ -108,7 +108,7 @@ CortexA76TC::readIntRegFlat(RegIndex idx) const if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) { orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR); ArmISA::CPSR new_cpsr = orig_cpsr; - new_cpsr.mode = MODE_MON; + new_cpsr.mode = ArmISA::MODE_MON; non_const_this->setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr); } @@ -129,7 +129,7 @@ CortexA76TC::setIntRegFlat(RegIndex idx, RegVal val) if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) { orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR); ArmISA::CPSR new_cpsr = orig_cpsr; - new_cpsr.mode = MODE_MON; + new_cpsr.mode = ArmISA::MODE_MON; setMiscReg(ArmISA::MISCREG_CPSR, new_cpsr); } @@ -146,7 +146,7 @@ CortexA76TC::readCCRegFlat(RegIndex idx) const RegVal result = Iris::ThreadContext::readCCRegFlat(idx); switch (idx) { case ArmISA::CCREG_NZ: - result = ((CPSR)result).nz; + result = ((ArmISA::CPSR)result).nz; break; case ArmISA::CCREG_FP: result = bits(result, 31, 28); @@ -163,14 +163,14 @@ CortexA76TC::setCCRegFlat(RegIndex idx, RegVal val) switch (idx) { case ArmISA::CCREG_NZ: { - CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR); + ArmISA::CPSR cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR); cpsr.nz = val; val = cpsr; } break; case ArmISA::CCREG_FP: { - FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR); + ArmISA::FPSCR fpscr = readMiscRegNoEffect(ArmISA::MISCREG_FPSCR); val = insertBits(fpscr, 31, 28, val); } break; @@ -921,10 +921,10 @@ Iris::ThreadContext::IdxNameMap CortexA76TC::flattenedIntIdxNameMap({ { ArmISA::INTREG_R13_FIQ, "X29" }, { ArmISA::INTREG_R14_FIQ, "X30" }, // Skip zero, ureg0-2, and dummy regs. - { INTREG_SP0, "SP_EL0" }, - { INTREG_SP1, "SP_EL1" }, - { INTREG_SP2, "SP_EL2" }, - { INTREG_SP3, "SP_EL3" }, + { ArmISA::INTREG_SP0, "SP_EL0" }, + { ArmISA::INTREG_SP1, "SP_EL1" }, + { ArmISA::INTREG_SP2, "SP_EL2" }, + { ArmISA::INTREG_SP3, "SP_EL3" }, }); Iris::ThreadContext::IdxNameMap CortexA76TC::ccRegIdxNameMap({ diff --git a/src/arch/arm/fastmodel/iris/interrupts.cc b/src/arch/arm/fastmodel/iris/interrupts.cc index 8c1f5b269d..197608901a 100644 --- a/src/arch/arm/fastmodel/iris/interrupts.cc +++ b/src/arch/arm/fastmodel/iris/interrupts.cc @@ -28,7 +28,7 @@ #include "arch/arm/fastmodel/iris/interrupts.hh" #include "arch/arm/fastmodel/iris/thread_context.hh" -#include "arch/arm/isa_traits.hh" +#include "arch/arm/interrupts.hh" #include "arch/arm/miscregs.hh" #include "arch/arm/miscregs_types.hh" #include "arch/arm/types.hh" @@ -86,12 +86,12 @@ Iris::Interrupts::serialize(CheckpointOut &cp) const for (bool &i: interrupts) i = false; - interrupts[INT_ABT] = phys_abort; - interrupts[INT_IRQ] = phys_irq; - interrupts[INT_FIQ] = phys_fiq; - interrupts[INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX); - interrupts[INT_VIRT_IRQ] = virt_irq; - interrupts[INT_VIRT_FIQ] = virt_fiq; + interrupts[ArmISA::INT_ABT] = phys_abort; + interrupts[ArmISA::INT_IRQ] = phys_irq; + interrupts[ArmISA::INT_FIQ] = phys_fiq; + interrupts[ArmISA::INT_SEV] = tc->readMiscReg(MISCREG_SEV_MAILBOX); + interrupts[ArmISA::INT_VIRT_IRQ] = virt_irq; + interrupts[ArmISA::INT_VIRT_FIQ] = virt_fiq; for (int i = 0; i < NumInterruptTypes; i++) { if (interrupts[i]) From 76bceca2e1366e8670f3dce08f0826adb50fdefc Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 24 Sep 2020 00:37:04 -0700 Subject: [PATCH 2/3] arm,fastmodel: Update the VExpressFastModel to use ArmInterruptPins. The HDLCD device now uses an ArmInterruptPin instead of a GIC and interrupt number parameter. Change-Id: I31122e66a1c18f61592f3dca214ee057baad8f88 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35039 Reviewed-by: Gabe Black Maintainer: Gabe Black Tested-by: kokoro --- src/dev/arm/VExpressFastmodel.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/dev/arm/VExpressFastmodel.py b/src/dev/arm/VExpressFastmodel.py index 8cf899436b..43f25efcf5 100644 --- a/src/dev/arm/VExpressFastmodel.py +++ b/src/dev/arm/VExpressFastmodel.py @@ -24,6 +24,7 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.objects.FastModelGIC import FastModelGIC, SCFastModelGIC +from m5.objects.Gic import ArmInterruptPin from m5.objects.RealView import VExpress_GEM5_Base, HDLcd class VExpressFastmodel(VExpress_GEM5_Base): @@ -35,7 +36,8 @@ class VExpressFastmodel(VExpress_GEM5_Base): )) hdlcd = HDLcd( - pxl_clk=VExpress_GEM5_Base.dcc.osc_pxl, pio_addr=0x2b000000, int_num=95) + pxl_clk=VExpress_GEM5_Base.dcc.osc_pxl, pio_addr=0x2b000000, + interrupt=ArmInterruptPin(num=95)) def __init__(self, *args, **kwargs): super(VExpressFastmodel, self).__init__(*args, **kwargs) From bcc797a2cb0cb8d4a2ca949d6693ca191c79d3c7 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Thu, 24 Sep 2020 00:36:21 -0700 Subject: [PATCH 3/3] fastmodel: Update the IRIS ThreadContext base class. The syscall() method has been removed, and HTM related methods have been added. Change-Id: I796c1a554bfd4b1ee01a62c9c7ad403dd699cc0f Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35038 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/arch/arm/fastmodel/iris/thread_context.hh | 24 ++++++++++++++----- 1 file changed, 18 insertions(+), 6 deletions(-) diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh index a37fbc6e26..2a64b5bf86 100644 --- a/src/arch/arm/fastmodel/iris/thread_context.hh +++ b/src/arch/arm/fastmodel/iris/thread_context.hh @@ -445,12 +445,6 @@ class ThreadContext : public ::ThreadContext panic("%s not implemented.", __FUNCTION__); } - void - syscall() override - { - panic("%s not implemented.", __FUNCTION__); - } - /** @{ */ /** * Flat register interfaces @@ -517,6 +511,24 @@ class ThreadContext : public ::ThreadContext void setCCRegFlat(RegIndex idx, RegVal val) override; /** @} */ + // hardware transactional memory + void + htmAbortTransaction(uint64_t htm_uid, HtmFailureFaultCause cause) override + { + panic("%s not implemented.", __FUNCTION__); + } + + BaseHTMCheckpointPtr & + getHtmCheckpointPtr() override + { + panic("%s not implemented.", __FUNCTION__); + } + + void + setHtmCheckpointPtr(BaseHTMCheckpointPtr cpt) override + { + panic("%s not implemented.", __FUNCTION__); + } }; } // namespace Iris