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Merge "misc: Merge branch 'release-staging-v21-0' into develop" into develop

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This commit is contained in:
Bobby R. Bruce
2021-03-11 04:55:39 +00:00
parent 49082c971f 8bb5d9fa11
commit 61bc567b0e
7 changed files with 66 additions and 18 deletions
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4
configs/common/MemConfig.py
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@@ -200,7 +200,7 @@ def config_mem(options, system):
if opt_mem_type and (not opt_nvm_type or range_iter % 2 != 0):
# Create the DRAM interface
dram_intf = create_mem_intf(intf, r, i, nbr_mem_ctrls,
intlv_bits, intlv_size, opt_xor_low_bit)
intlv_bits, intlv_size, opt_xor_low_bit)
# Set the number of ranks based on the command-line
# options if it was explicitly set
@@ -241,7 +241,7 @@ def config_mem(options, system):
elif opt_nvm_type and (not opt_mem_type or range_iter % 2 == 0):
nvm_intf = create_mem_intf(n_intf, r, i, nbr_mem_ctrls,
intlv_bits, intlv_size)
intlv_bits, intlv_size, opt_xor_low_bit)
# Set the number of ranks based on the command-line
# options if it was explicitly set
if issubclass(n_intf, m5.objects.NVMInterface) and \

3
src/arch/arm/tlb.cc
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@@ -872,8 +872,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
// sctlr.wxn overrides the xn bit
grant = !wxn && !xn;
} else if (is_atomic) {
grant = r && w;
grant_read = r;
grant = hap;
} else if (is_write) {
grant = hap & 0x2;
} else { // is_read

2
src/arch/gcn3/insts/instructions.cc
View File

@@ -4114,8 +4114,6 @@ namespace Gcn3ISA
if (wf->hasBarrier()) {
int bar_id = wf->barrierId();
assert(wf->getStatus() != Wavefront::S_BARRIER);
wf->setStatus(Wavefront::S_BARRIER);
cu->incNumAtBarrier(bar_id);
DPRINTF(GPUSync, "CU[%d] WF[%d][%d] Wave[%d] - Stalling at "
"barrier Id%d. %d waves now at barrier, %d waves "

3
src/gpu-compute/schedule_stage.cc
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@@ -314,6 +314,9 @@ ScheduleStage::addToSchList(int exeType, const GPUDynInstPtr &gpu_dyn_inst)
computeUnit.insertInPipeMap(wf);
wavesInSch.emplace(wf->wfDynId);
schList.at(exeType).push_back(std::make_pair(gpu_dyn_inst, RFBUSY));
if (wf->isOldestInstBarrier() && wf->hasBarrier()) {
wf->setStatus(Wavefront::S_BARRIER);
}
if (wf->isOldestInstWaitcnt()) {
wf->setStatus(Wavefront::S_WAITCNT);
}

68
src/python/m5/ext/pystats/group.py
View File

@@ -24,7 +24,8 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from typing import Dict, Iterator, List, Optional, Union
import re
from typing import Callable, Dict, Iterator, List, Optional, Pattern, Union
from .jsonserializable import JsonSerializable
from .statistic import Scalar, Statistic
@@ -53,25 +54,72 @@ class Group(JsonSerializable):
for key,value in kwargs.items():
setattr(self, key, value)
def children(self, predicate: Optional[Callable[[str], bool]] = None
) -> Iterator[Union["Group", Statistic]]:
""" Iterate through all of the children, optionally with a predicate
```
>>> system.children(lambda _name: 'cpu' in name)
[cpu0, cpu1, cpu2]
```
:param: predicate(str) -> bool: Optional. Each child's name is passed
to this function. If it returns true, then the child is
yielded. Otherwise, the child is skipped.
If not provided then all children are returned.
"""
for attr in self.__dict__:
# Check the provided predicate. If not a match, skip this child
if predicate and not predicate(attr): continue
obj = getattr(self, attr)
if isinstance(obj, Group) or isinstance(obj, Statistic):
yield obj
def find(self, name: str) -> Iterator[Union["Group", Statistic]]:
""" Find all stats that match the name
This function searches all of the "children" in this group. It yields
the set of attributes (children) that have the `name` as a substring.
The order of the objects returned by the generator is arbitrary.
```
system.find('cpu') -> [cpu0, cpu1, cpu2, cpu3, other_cpu, ...]
>>> system.find('cpu')
[cpu0, cpu1, cpu2, cpu3, other_cpu, ...]
```
This is useful for performing aggregates over substats. For instance:
```
total_instruuctions = sum([cpu.exec_context.thread_0.numInsts.value
for cpu in simstat.system.find('cpu')])
>>> total_instructions = sum([cpu.exec_context.thread_0.numInsts.value
for cpu in simstat.system.find('cpu')])
100000
```
:param: name: The name to search for
"""
for attr in self.__dict__:
if name in attr:
obj = getattr(self, attr)
if isinstance(obj, Group) or isinstance(obj, Statistic):
yield obj
yield from self.children(lambda _name: _name in name)
def find_re(self, regex: Union[str, Pattern]
) -> Iterator[Union["Group", Statistic]]:
""" Find all stats that match the name
This function searches all of the "children" in this group. It yields
the set of attributes (children) that have the `name` mathing the
regex provided. The order of the objects returned by the generator is
arbitrary.
```
>>> system.find_re('cpu[0-9]')
[cpu0, cpu1, cpu2]
```
Note: The above will not match `cpu_other`.
:param: regex: The regular expression used to search. Can be a
precompiled regex or a string in regex format
"""
if isinstance(regex, str):
regex = re.compile(regex)
yield from self.children(lambda _name: regex.search(_name))
class Vector(Group):
"""
@@ -86,4 +134,4 @@ class Vector(Group):
type="Vector",
time_conversion=None,
**scalar_map,
)
)

2
system/arm/dt/armv8.dts
View File

@@ -38,7 +38,7 @@
compatible = "gem5,armv8", "arm,armv8"; \
reg = < n >; \
enable-method = "spin-table"; \
cpu-release-addr = <0 0x8000fff8>; \
cpu-release-addr = <0 0x87fffff8>; \
};
/ {

2
system/arm/dt/armv8_big_little.dts
View File

@@ -46,7 +46,7 @@
compatible = "gem5,armv8", "arm,armv8"; \
reg = < ## id >; \
enable-method = "spin-table"; \
cpu-release-addr = <0 0x8000fff8>; \
cpu-release-addr = <0 0x87fffff8>; \
};