diff --git a/configs/common/MemConfig.py b/configs/common/MemConfig.py
index 6e78be5291..b8907c0ac7 100644
--- a/configs/common/MemConfig.py
+++ b/configs/common/MemConfig.py
@@ -200,7 +200,7 @@ def config_mem(options, system):
             if opt_mem_type and (not opt_nvm_type or range_iter % 2 != 0):
                 # Create the DRAM interface
                 dram_intf = create_mem_intf(intf, r, i, nbr_mem_ctrls,
-                                    intlv_bits, intlv_size, opt_xor_low_bit)
+                    intlv_bits, intlv_size, opt_xor_low_bit)
 
                 # Set the number of ranks based on the command-line
                 # options if it was explicitly set
@@ -241,7 +241,7 @@ def config_mem(options, system):
 
             elif opt_nvm_type and (not opt_mem_type or range_iter % 2 == 0):
                 nvm_intf = create_mem_intf(n_intf, r, i, nbr_mem_ctrls,
-                                           intlv_bits, intlv_size)
+                    intlv_bits, intlv_size, opt_xor_low_bit)
                 # Set the number of ranks based on the command-line
                 # options if it was explicitly set
                 if issubclass(n_intf, m5.objects.NVMInterface) and \
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index fd72d258b9..8e5b3ca9b8 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -872,8 +872,7 @@ TLB::checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode,
             // sctlr.wxn overrides the xn bit
             grant = !wxn && !xn;
         } else if (is_atomic) {
-            grant = r && w;
-            grant_read = r;
+            grant = hap;
         } else if (is_write) {
             grant = hap & 0x2;
         } else { // is_read
diff --git a/src/arch/gcn3/insts/instructions.cc b/src/arch/gcn3/insts/instructions.cc
index 29de1a8a95..bde87efeea 100644
--- a/src/arch/gcn3/insts/instructions.cc
+++ b/src/arch/gcn3/insts/instructions.cc
@@ -4114,8 +4114,6 @@ namespace Gcn3ISA
 
         if (wf->hasBarrier()) {
             int bar_id = wf->barrierId();
-            assert(wf->getStatus() != Wavefront::S_BARRIER);
-            wf->setStatus(Wavefront::S_BARRIER);
             cu->incNumAtBarrier(bar_id);
             DPRINTF(GPUSync, "CU[%d] WF[%d][%d] Wave[%d] - Stalling at "
                     "barrier Id%d. %d waves now at barrier, %d waves "
diff --git a/src/gpu-compute/schedule_stage.cc b/src/gpu-compute/schedule_stage.cc
index 8a2ea18294..ace6d0c3f5 100644
--- a/src/gpu-compute/schedule_stage.cc
+++ b/src/gpu-compute/schedule_stage.cc
@@ -314,6 +314,9 @@ ScheduleStage::addToSchList(int exeType, const GPUDynInstPtr &gpu_dyn_inst)
         computeUnit.insertInPipeMap(wf);
         wavesInSch.emplace(wf->wfDynId);
         schList.at(exeType).push_back(std::make_pair(gpu_dyn_inst, RFBUSY));
+        if (wf->isOldestInstBarrier() && wf->hasBarrier()) {
+            wf->setStatus(Wavefront::S_BARRIER);
+        }
         if (wf->isOldestInstWaitcnt()) {
             wf->setStatus(Wavefront::S_WAITCNT);
         }
diff --git a/src/python/m5/ext/pystats/group.py b/src/python/m5/ext/pystats/group.py
index 10887e20a1..22d11b2702 100644
--- a/src/python/m5/ext/pystats/group.py
+++ b/src/python/m5/ext/pystats/group.py
@@ -24,7 +24,8 @@
 # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
-from typing import Dict, Iterator, List, Optional, Union
+import re
+from typing import Callable, Dict, Iterator, List, Optional, Pattern, Union
 
 from .jsonserializable import JsonSerializable
 from .statistic import Scalar, Statistic
@@ -53,25 +54,72 @@ class Group(JsonSerializable):
         for key,value in kwargs.items():
             setattr(self, key, value)
 
+    def children(self, predicate: Optional[Callable[[str], bool]] = None
+                 ) -> Iterator[Union["Group", Statistic]]:
+        """ Iterate through all of the children, optionally with a predicate
+
+        ```
+        >>> system.children(lambda _name: 'cpu' in name)
+        [cpu0, cpu1, cpu2]
+        ```
+
+        :param: predicate(str) -> bool: Optional. Each child's name is passed
+                to this function. If it returns true, then the child is
+                yielded. Otherwise, the child is skipped.
+                If not provided then all children are returned.
+        """
+        for attr in self.__dict__:
+            # Check the provided predicate. If not a match, skip this child
+            if predicate and not predicate(attr): continue
+            obj = getattr(self, attr)
+            if isinstance(obj, Group) or isinstance(obj, Statistic):
+                yield obj
+
     def find(self, name: str) -> Iterator[Union["Group", Statistic]]:
         """ Find all stats that match the name
+
         This function searches all of the "children" in this group. It yields
         the set of attributes (children) that have the `name` as a substring.
         The order of the objects returned by the generator is arbitrary.
+
         ```
-        system.find('cpu') -> [cpu0, cpu1, cpu2, cpu3, other_cpu, ...]
+        >>> system.find('cpu')
+        [cpu0, cpu1, cpu2, cpu3, other_cpu, ...]
         ```
+
         This is useful for performing aggregates over substats. For instance:
+
         ```
-        total_instruuctions = sum([cpu.exec_context.thread_0.numInsts.value
-                                   for cpu in simstat.system.find('cpu')])
+        >>> total_instructions = sum([cpu.exec_context.thread_0.numInsts.value
+                                      for cpu in simstat.system.find('cpu')])
+        100000
         ```
+
+        :param: name: The name to search for
         """
-        for attr in self.__dict__:
-            if name in attr:
-                obj = getattr(self, attr)
-                if isinstance(obj, Group) or isinstance(obj, Statistic):
-                    yield obj
+        yield from self.children(lambda _name: _name in name)
+
+    def find_re(self, regex: Union[str, Pattern]
+                ) -> Iterator[Union["Group", Statistic]]:
+        """ Find all stats that match the name
+
+        This function searches all of the "children" in this group. It yields
+        the set of attributes (children) that have the `name` mathing the
+        regex provided. The order of the objects returned by the generator is
+        arbitrary.
+
+        ```
+        >>> system.find_re('cpu[0-9]')
+        [cpu0, cpu1, cpu2]
+        ```
+        Note: The above will not match `cpu_other`.
+
+        :param: regex: The regular expression used to search. Can be a
+                precompiled regex or a string in regex format
+        """
+        if isinstance(regex, str):
+            regex = re.compile(regex)
+        yield from self.children(lambda _name: regex.search(_name))
 
 class Vector(Group):
     """
@@ -86,4 +134,4 @@ class Vector(Group):
                                      type="Vector",
                                      time_conversion=None,
                                      **scalar_map,
-                                    )
\ No newline at end of file
+                                    )
diff --git a/system/arm/dt/armv8.dts b/system/arm/dt/armv8.dts
index 42c6ef654f..6ea7820e8d 100644
--- a/system/arm/dt/armv8.dts
+++ b/system/arm/dt/armv8.dts
@@ -38,7 +38,7 @@
 		compatible = "gem5,armv8", "arm,armv8"; \
 		reg = < n >; \
 		enable-method = "spin-table"; \
-		cpu-release-addr = <0 0x8000fff8>; \
+		cpu-release-addr = <0 0x87fffff8>; \
 	};
 
 / {
diff --git a/system/arm/dt/armv8_big_little.dts b/system/arm/dt/armv8_big_little.dts
index 9d1e7acfd9..39d6d9b17f 100644
--- a/system/arm/dt/armv8_big_little.dts
+++ b/system/arm/dt/armv8_big_little.dts
@@ -46,7 +46,7 @@
 		compatible = "gem5,armv8", "arm,armv8"; \
 		reg = < ## id >; \
 		enable-method = "spin-table"; \
-		cpu-release-addr = <0 0x8000fff8>; \
+		cpu-release-addr = <0 0x87fffff8>; \
 	};