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arch-vega: Fix V_READFIRSTLANE_B32

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This instruction appears to be the only VOP1 instruction that has a
scalar destination using VDST as the destination register number.
However, since VDST is only 8 bits it cannot encode all possible
registers. Therefore, use the opcode to determine if the destination is
a scalar or vector destination.

This issue manifests as a VGPR dest being out of range for a kernel
where the number of SGPRs is more than the number of VGPRs and the
intended SGPR dest is larger than the count of VGPRs

Change-Id: I95a7de1ddb97f7171f48331fed36aef776fa0cb4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61649
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Matthew Poremba
2022-01-27 16:53:36 -08:00
parent 1c423ad7e6
commit 618d16d6fc
1 changed files with 15 additions and 2 deletions
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17
src/arch/amdgpu/vega/insts/op_encodings.cc
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@@ -772,8 +772,21 @@ namespace VegaISA
if (numDstRegOperands()) {
reg = instData.VDST;
dstOps.emplace_back(reg, getOperandSize(opNum), false,
false, true, false);
/*
The v_readfirstlane_b32 instruction (op = 2) is a special case
VOP1 instruction which has a scalar register as the destination.
(See section 6.6.2 "Special Cases" in the Vega ISA manual)
Therefore we change the dest op to be scalar reg = true and
vector reg = false in reserve of all other instructions.
*/
if (instData.OP == 2) {
dstOps.emplace_back(reg, getOperandSize(opNum), false,
true, false, false);
} else {
dstOps.emplace_back(reg, getOperandSize(opNum), false,
false, true, false);
}
}
assert(srcOps.size() == numSrcRegOperands());