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arch-arm: Remove MISCREG_INFO E2H flag

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These VHE flags are not needed anymore.

They were used to trap EL2 access to VHE only registers (like CPACR_EL12)
when VHE was disabled (hcr.e2h = 0)

With the new faulting logic, we can just introduce VHE specific
callbacks checking for the hcr.e2h bitfield and returning an undefined
instruction if VHE is disabled.

In this way we don't have to add VHE only bits to every system register

Change-Id: I07bf9a9adc7a089bd45e718fb06d88488a2b7ed5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/61678
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2022-07-13 23:39:09 +01:00
parent 9bd4520b13
commit 1c423ad7e6
2 changed files with 63 additions and 192 deletions
Download Patch File Download Diff File Expand all files Collapse all files

151
src/arch/arm/regs/misc.cc
View File

@@ -1290,69 +1290,28 @@ MiscRegLUTEntry::defaultFault(const MiscRegLUTEntry &entry,
}
}
Fault
MiscRegLUTEntry::defaultReadFaultEL2(const MiscRegLUTEntry &entry,
static Fault
defaultFaultE2H_EL2(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const bool el2_host = EL2Enabled(tc) && hcr.e2h;
if (el2_host) {
return defaultFault<MISCREG_HYP_E2H_S_RD, MISCREG_HYP_E2H_NS_RD>(
entry, tc, inst);
if (hcr.e2h) {
return NoFault;
} else {
return defaultFault<MISCREG_HYP_S_RD, MISCREG_HYP_NS_RD>(
entry, tc, inst);
return inst.undefined();
}
}
Fault
MiscRegLUTEntry::defaultWriteFaultEL2(const MiscRegLUTEntry &entry,
static Fault
defaultFaultE2H_EL3(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const bool el2_host = EL2Enabled(tc) && hcr.e2h;
if (el2_host) {
return defaultFault<MISCREG_HYP_E2H_S_WR, MISCREG_HYP_E2H_NS_WR>(
entry, tc, inst);
return NoFault;
} else {
return defaultFault<MISCREG_HYP_S_WR, MISCREG_HYP_NS_WR>(
entry, tc, inst);
}
}
Fault
MiscRegLUTEntry::defaultReadFaultEL3(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const bool el2_host = EL2Enabled(tc) && hcr.e2h;
if (el2_host) {
if (entry.info[MISCREG_MON_E2H_RD]) {
return NoFault;
} else {
return inst.undefined();
}
} else {
return defaultFault<MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD>(
entry, tc, inst);
}
}
Fault
MiscRegLUTEntry::defaultWriteFaultEL3(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst)
{
const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
const bool el2_host = EL2Enabled(tc) && hcr.e2h;
if (el2_host) {
if (entry.info[MISCREG_MON_E2H_WR]) {
return NoFault;
} else {
return inst.undefined();
}
} else {
return defaultFault<MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR>(
entry, tc, inst);
return inst.undefined();
}
}
@@ -2797,8 +2756,8 @@ ISA::initializeMiscRegMetadata()
| (LSMAOE ? 0 : 0x10000000))
.mapsTo(MISCREG_SCTLR_NS);
InitReg(MISCREG_SCTLR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.res0( 0x20440 | (EnDB ? 0 : 0x2000)
| (IESB ? 0 : 0x200000)
| (EnDA ? 0 : 0x8000000)
@@ -2815,8 +2774,8 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_CPACR);
InitReg(MISCREG_CPACR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_CPACR_EL1);
InitReg(MISCREG_SCTLR_EL2)
.hyp().mon()
@@ -2870,22 +2829,22 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_TTBR0_NS);
InitReg(MISCREG_TTBR0_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_TTBR0_EL1);
InitReg(MISCREG_TTBR1_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_TTBR1_NS);
InitReg(MISCREG_TTBR1_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_TTBR1_EL1);
InitReg(MISCREG_TCR_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_TTBCR_NS);
InitReg(MISCREG_TCR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_TTBCR_NS);
InitReg(MISCREG_TTBR0_EL2)
.hyp().mon()
@@ -2916,14 +2875,14 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_SPSR_SVC); // NAM C5.2.17 SPSR_EL1
InitReg(MISCREG_SPSR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_SPSR_SVC);
InitReg(MISCREG_ELR_EL1)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_ELR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_ELR_EL1);
InitReg(MISCREG_SP_EL0)
.allPrivileges().exceptUserMode();
@@ -2974,21 +2933,21 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_ADFSR_NS);
InitReg(MISCREG_AFSR0_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_ADFSR_NS);
InitReg(MISCREG_AFSR1_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_AIFSR_NS);
InitReg(MISCREG_AFSR1_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_AIFSR_NS);
InitReg(MISCREG_ESR_EL1)
.allPrivileges().exceptUserMode();
InitReg(MISCREG_ESR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_ESR_EL1);
InitReg(MISCREG_IFSR32_EL2)
.hyp().mon()
@@ -3014,8 +2973,8 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
InitReg(MISCREG_FAR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_DFAR_NS, MISCREG_IFAR_NS);
InitReg(MISCREG_FAR_EL2)
.hyp().mon()
@@ -3199,15 +3158,15 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
InitReg(MISCREG_MAIR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_PRRR_NS, MISCREG_NMRR_NS);
InitReg(MISCREG_AMAIR_EL1)
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
InitReg(MISCREG_AMAIR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_AMAIR0_NS, MISCREG_AMAIR1_NS);
InitReg(MISCREG_MAIR_EL2)
.hyp().mon()
@@ -3227,8 +3186,8 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_VBAR_NS);
InitReg(MISCREG_VBAR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_VBAR_NS);
InitReg(MISCREG_RVBAR_EL1)
.privRead(FullSystem && system->highestEL() == EL1);
@@ -3250,8 +3209,8 @@ ISA::initializeMiscRegMetadata()
.allPrivileges().exceptUserMode()
.mapsTo(MISCREG_CONTEXTIDR_NS);
InitReg(MISCREG_CONTEXTIDR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_CONTEXTIDR_NS);
InitReg(MISCREG_TPIDR_EL1)
.allPrivileges().exceptUserMode()
@@ -3304,31 +3263,31 @@ ISA::initializeMiscRegMetadata()
.res0(0xffffffff00000000)
.mapsTo(MISCREG_CNTV_TVAL);
InitReg(MISCREG_CNTP_CTL_EL02)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.res0(0xfffffffffffffff8)
.mapsTo(MISCREG_CNTP_CTL_NS);
InitReg(MISCREG_CNTP_CVAL_EL02)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_CNTP_CVAL_NS);
InitReg(MISCREG_CNTP_TVAL_EL02)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.res0(0xffffffff00000000)
.mapsTo(MISCREG_CNTP_TVAL_NS);
InitReg(MISCREG_CNTV_CTL_EL02)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.res0(0xfffffffffffffff8)
.mapsTo(MISCREG_CNTV_CTL);
InitReg(MISCREG_CNTV_CVAL_EL02)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_CNTV_CVAL);
InitReg(MISCREG_CNTV_TVAL_EL02)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.res0(0xffffffff00000000)
.mapsTo(MISCREG_CNTV_TVAL);
InitReg(MISCREG_CNTKCTL_EL1)
@@ -3337,8 +3296,8 @@ ISA::initializeMiscRegMetadata()
.res0(0xfffffffffffdfc00)
.mapsTo(MISCREG_CNTKCTL);
InitReg(MISCREG_CNTKCTL_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.res0(0xfffffffffffdfc00)
.mapsTo(MISCREG_CNTKCTL);
InitReg(MISCREG_CNTPS_CTL_EL1)
@@ -3967,8 +3926,8 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_ZCR_EL2)
.hyp().mon();
InitReg(MISCREG_ZCR_EL12)
.monE2H()
.hypE2H()
.fault(EL2, defaultFaultE2H_EL2)
.fault(EL3, defaultFaultE2H_EL3)
.mapsTo(MISCREG_ZCR_EL1);
InitReg(MISCREG_ZCR_EL1)
.allPrivileges().exceptUserMode();

104
src/arch/arm/regs/misc.hh
View File

@@ -1136,20 +1136,12 @@ namespace ArmISA
MISCREG_HYP_NS_WR,
MISCREG_HYP_S_RD,
MISCREG_HYP_S_WR,
// Hypervisor mode, HCR_EL2.E2H == 1
MISCREG_HYP_E2H_NS_RD,
MISCREG_HYP_E2H_NS_WR,
MISCREG_HYP_E2H_S_RD,
MISCREG_HYP_E2H_S_WR,
// Monitor mode, SCR.NS == 0
MISCREG_MON_NS0_RD,
MISCREG_MON_NS0_WR,
// Monitor mode, SCR.NS == 1
MISCREG_MON_NS1_RD,
MISCREG_MON_NS1_WR,
// Monitor mode, HCR_EL2.E2H == 1
MISCREG_MON_E2H_RD,
MISCREG_MON_E2H_WR,
NUM_MISCREG_INFOS
};
@@ -1181,27 +1173,19 @@ namespace ArmISA
template <MiscRegInfo Sec, MiscRegInfo NonSec>
static Fault defaultFault(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst);
static Fault defaultReadFaultEL2(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst);
static Fault defaultWriteFaultEL2(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst);
static Fault defaultReadFaultEL3(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst);
static Fault defaultWriteFaultEL3(const MiscRegLUTEntry &entry,
ThreadContext *tc, const MiscRegOp64 &inst);
public:
MiscRegLUTEntry() :
lower(0), upper(0),
_reset(0), _res0(0), _res1(0), _raz(0), _rao(0), info(0),
faultRead({ defaultFault<MISCREG_USR_S_RD, MISCREG_USR_NS_RD>,
defaultFault<MISCREG_PRI_S_RD, MISCREG_PRI_NS_RD>,
defaultReadFaultEL2,
defaultReadFaultEL3 }),
faultWrite({ defaultFault<MISCREG_USR_S_WR, MISCREG_USR_NS_WR>,
defaultFault<MISCREG_PRI_S_WR, MISCREG_PRI_NS_WR>,
defaultWriteFaultEL2,
defaultWriteFaultEL3 })
faultRead({defaultFault<MISCREG_USR_S_RD, MISCREG_USR_NS_RD>,
defaultFault<MISCREG_PRI_S_RD, MISCREG_PRI_NS_RD>,
defaultFault<MISCREG_HYP_S_RD, MISCREG_HYP_NS_RD>,
defaultFault<MISCREG_MON_NS0_RD, MISCREG_MON_NS1_RD>}),
faultWrite({defaultFault<MISCREG_USR_S_WR, MISCREG_USR_NS_WR>,
defaultFault<MISCREG_PRI_S_WR, MISCREG_PRI_NS_WR>,
defaultFault<MISCREG_HYP_S_WR, MISCREG_HYP_NS_WR>,
defaultFault<MISCREG_MON_NS0_WR, MISCREG_MON_NS1_WR>})
{}
uint64_t reset() const { return _reset; }
uint64_t res0() const { return _res0; }
@@ -1382,51 +1366,6 @@ namespace ArmISA
return *this;
}
chain
hypE2HSecureRead(bool v = true) const
{
entry.info[MISCREG_HYP_E2H_S_RD] = v;
return *this;
}
chain
hypE2HNonSecureRead(bool v = true) const
{
entry.info[MISCREG_HYP_E2H_NS_RD] = v;
return *this;
}
chain
hypE2HRead(bool v = true) const
{
hypE2HSecureRead(v);
hypE2HNonSecureRead(v);
return *this;
}
chain
hypE2HSecureWrite(bool v = true) const
{
entry.info[MISCREG_HYP_E2H_S_WR] = v;
return *this;
}
chain
hypE2HNonSecureWrite(bool v = true) const
{
entry.info[MISCREG_HYP_E2H_NS_WR] = v;
return *this;
}
chain
hypE2HWrite(bool v = true) const
{
hypE2HSecureWrite(v);
hypE2HNonSecureWrite(v);
return *this;
}
chain
hypE2H(bool v = true) const
{
hypE2HRead(v);
hypE2HWrite(v);
return *this;
}
chain
hypSecureRead(bool v = true) const
{
entry.info[MISCREG_HYP_S_RD] = v;
@@ -1441,7 +1380,6 @@ namespace ArmISA
chain
hypRead(bool v = true) const
{
hypE2HRead(v);
hypSecureRead(v);
hypNonSecureRead(v);
return *this;
@@ -1461,7 +1399,6 @@ namespace ArmISA
chain
hypWrite(bool v = true) const
{
hypE2HWrite(v);
hypSecureWrite(v);
hypNonSecureWrite(v);
return *this;
@@ -1469,8 +1406,6 @@ namespace ArmISA
chain
hypSecure(bool v = true) const
{
hypE2HSecureRead(v);
hypE2HSecureWrite(v);
hypSecureRead(v);
hypSecureWrite(v);
return *this;
@@ -1483,49 +1418,26 @@ namespace ArmISA
return *this;
}
chain
monE2HRead(bool v = true) const
{
entry.info[MISCREG_MON_E2H_RD] = v;
return *this;
}
chain
monE2HWrite(bool v = true) const
{
entry.info[MISCREG_MON_E2H_WR] = v;
return *this;
}
chain
monE2H(bool v = true) const
{
monE2HRead(v);
monE2HWrite(v);
return *this;
}
chain
monSecureRead(bool v = true) const
{
monE2HRead(v);
entry.info[MISCREG_MON_NS0_RD] = v;
return *this;
}
chain
monSecureWrite(bool v = true) const
{
monE2HWrite(v);
entry.info[MISCREG_MON_NS0_WR] = v;
return *this;
}
chain
monNonSecureRead(bool v = true) const
{
monE2HRead(v);
entry.info[MISCREG_MON_NS1_RD] = v;
return *this;
}
chain
monNonSecureWrite(bool v = true) const
{
monE2HWrite(v);
entry.info[MISCREG_MON_NS1_WR] = v;
return *this;
}