mem-ruby: Allow Addr as a controller member type

Change-Id: I63127ed06b4f871b74faad6c2c6436aebd118334 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
2023-06-29 09:55:12 +01:00
parent f7d6dadc10
commit 5dbc48432f
1 changed files with 1 additions and 0 deletions
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -64,6 +64,7 @@ python_class_map = {
    "DMASequencer": "DMASequencer",
    "RubyPrefetcher": "RubyPrefetcher",
    "Cycles": "Cycles",
+    "Addr": "Addr",
 }