From 5dbc48432f121f6849e7cb079295fe4dc815205f Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Thu, 29 Jun 2023 09:55:12 +0100
Subject: [PATCH] mem-ruby: Allow Addr as a controller member type

Change-Id: I63127ed06b4f871b74faad6c2c6436aebd118334
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
---
 src/mem/slicc/symbols/StateMachine.py | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 039202a321..20ab096a63 100644
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -64,6 +64,7 @@ python_class_map = {
     "DMASequencer": "DMASequencer",
     "RubyPrefetcher": "RubyPrefetcher",
     "Cycles": "Cycles",
+    "Addr": "Addr",
 }