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util: Fix recent cpt_upgraders not checking for ISA

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A set of cpt_upgraders was patching old checkpoints regardless
of the ISA in use. Thanks to the previous patch, we can now
retrieve the ISA of the CPU from the isa section.

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Ia110068c06453796cefac028ee13f21667e5371a
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
This commit is contained in:
Giacomo Travaglini
2024-02-15 17:39:04 +00:00
parent 3d2052bc03
commit 5bce5673b0
3 changed files with 55 additions and 10 deletions
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20
util/cpt_upgraders/riscv-dyn-vlen.py
View File

@@ -1,3 +1,15 @@
# Copyright (c) 2024 Arm Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2023 Barcelona Supercomputing Center (BSC)
# All rights reserved.
@@ -35,12 +47,14 @@ def upgrader(cpt):
VecRegContainer is always MaxVecLenInBytes.
"""
for sec in cpt.sections():
import re
import re
for sec in cpt.sections():
# Search for all XC sections
if re.search(r".*processor.*\.core.*\.xc.*", sec):
res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec)
if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv":
# Only update for RISCV XCs
# Updating RVV vector registers (dummy values)
mr = cpt.get(sec, "regs.vector").split()
if len(mr) != 327680:

20
util/cpt_upgraders/riscv-pcstate.py
View File

@@ -1,3 +1,15 @@
# Copyright (c) 2024 Arm Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2023 Google LLC
# All rights reserved.
@@ -29,10 +41,12 @@ def upgrader(cpt):
# Update the RISC-V pcstate to match the new version of
# PCState
for sec in cpt.sections():
import re
import re
if re.search(r".*processor.*\.core.*\.xc.*", sec):
for sec in cpt.sections():
res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec)
if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv":
# Only update for RISCV XCs
if cpt.get(sec, "_rvType", fallback="") == "":
cpt.set(sec, "_rvType", "1")

25
util/cpt_upgraders/riscv-vext.py
View File

@@ -1,3 +1,15 @@
# Copyright (c) 2024 Arm Limited
# All rights reserved
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2023 Barcelona Supercomputing Center (BSC)
# All rights reserved.
@@ -35,11 +47,13 @@ def upgrader(cpt):
3) Add RVV misc registers in the checkpoint
"""
for sec in cpt.sections():
import re
import re
for sec in cpt.sections():
# Search for all XC sections
if re.search(r".*processor.*\.core.*\.xc.*", sec):
res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec)
if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv":
# Only update for RISCV XCs
# Updating RVV vector registers (dummy values)
# Assuming VLEN = 256 bits (32 bytes)
mr = cpt.get(sec, "regs.vector").split()
@@ -56,7 +70,10 @@ def upgrader(cpt):
cpt.set(sec, "regs.matrix", "")
# Search for all ISA sections
if re.search(r".*processor.*\.core.*\.isa$", sec):
if (
re.search(r".*processor.*\.core.*\.isa$", sec)
and cpt.get(sec, "isaName") == "riscv"
):
# Updating RVV misc registers (dummy values)
mr = cpt.get(sec, "miscRegFile").split()
if len(mr) == 164: