From 5bce5673b0dcf7a7f9c8e8df99bf4e9ea5f98598 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Thu, 15 Feb 2024 17:39:04 +0000 Subject: [PATCH] util: Fix recent cpt_upgraders not checking for ISA A set of cpt_upgraders was patching old checkpoints regardless of the ISA in use. Thanks to the previous patch, we can now retrieve the ISA of the CPU from the isa section. Signed-off-by: Giacomo Travaglini Change-Id: Ia110068c06453796cefac028ee13f21667e5371a Reviewed-by: Richard Cooper --- util/cpt_upgraders/riscv-dyn-vlen.py | 20 +++++++++++++++++--- util/cpt_upgraders/riscv-pcstate.py | 20 +++++++++++++++++--- util/cpt_upgraders/riscv-vext.py | 25 +++++++++++++++++++++---- 3 files changed, 55 insertions(+), 10 deletions(-) diff --git a/util/cpt_upgraders/riscv-dyn-vlen.py b/util/cpt_upgraders/riscv-dyn-vlen.py index ea2de9d19d..bac38173e5 100644 --- a/util/cpt_upgraders/riscv-dyn-vlen.py +++ b/util/cpt_upgraders/riscv-dyn-vlen.py @@ -1,3 +1,15 @@ +# Copyright (c) 2024 Arm Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2023 Barcelona Supercomputing Center (BSC) # All rights reserved. @@ -35,12 +47,14 @@ def upgrader(cpt): VecRegContainer is always MaxVecLenInBytes. """ - for sec in cpt.sections(): - import re + import re + for sec in cpt.sections(): # Search for all XC sections - if re.search(r".*processor.*\.core.*\.xc.*", sec): + res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec) + if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv": + # Only update for RISCV XCs # Updating RVV vector registers (dummy values) mr = cpt.get(sec, "regs.vector").split() if len(mr) != 327680: diff --git a/util/cpt_upgraders/riscv-pcstate.py b/util/cpt_upgraders/riscv-pcstate.py index 4182355419..e2bc951941 100644 --- a/util/cpt_upgraders/riscv-pcstate.py +++ b/util/cpt_upgraders/riscv-pcstate.py @@ -1,3 +1,15 @@ +# Copyright (c) 2024 Arm Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2023 Google LLC # All rights reserved. @@ -29,10 +41,12 @@ def upgrader(cpt): # Update the RISC-V pcstate to match the new version of # PCState - for sec in cpt.sections(): - import re + import re - if re.search(r".*processor.*\.core.*\.xc.*", sec): + for sec in cpt.sections(): + res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec) + if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv": + # Only update for RISCV XCs if cpt.get(sec, "_rvType", fallback="") == "": cpt.set(sec, "_rvType", "1") diff --git a/util/cpt_upgraders/riscv-vext.py b/util/cpt_upgraders/riscv-vext.py index d335f74b83..7012a4b3f6 100644 --- a/util/cpt_upgraders/riscv-vext.py +++ b/util/cpt_upgraders/riscv-vext.py @@ -1,3 +1,15 @@ +# Copyright (c) 2024 Arm Limited +# All rights reserved +# +# The license below extends only to copyright in the software and shall +# not be construed as granting a license to any other intellectual +# property including but not limited to intellectual property relating +# to a hardware implementation of the functionality of the software +# licensed hereunder. You may use the software subject to the license +# terms below provided that you ensure that this notice is replicated +# unmodified and in its entirety in all distributions of the software, +# modified or unmodified, in source code or in binary form. +# # Copyright (c) 2023 Barcelona Supercomputing Center (BSC) # All rights reserved. @@ -35,11 +47,13 @@ def upgrader(cpt): 3) Add RVV misc registers in the checkpoint """ - for sec in cpt.sections(): - import re + import re + for sec in cpt.sections(): # Search for all XC sections - if re.search(r".*processor.*\.core.*\.xc.*", sec): + res = re.search(r"(.*processor.*\.core.*)\.xc.*", sec) + if res and cpt.get(res.groups()[0] + ".isa", "isaName") == "riscv": + # Only update for RISCV XCs # Updating RVV vector registers (dummy values) # Assuming VLEN = 256 bits (32 bytes) mr = cpt.get(sec, "regs.vector").split() @@ -56,7 +70,10 @@ def upgrader(cpt): cpt.set(sec, "regs.matrix", "") # Search for all ISA sections - if re.search(r".*processor.*\.core.*\.isa$", sec): + if ( + re.search(r".*processor.*\.core.*\.isa$", sec) + and cpt.get(sec, "isaName") == "riscv" + ): # Updating RVV misc registers (dummy values) mr = cpt.get(sec, "miscRegFile").split() if len(mr) == 164: