dev-arm: Remove the SMMUv3 irq_interface_enable parameter

The SMMU_IRQ_CTRL had been made optionally writeable by a
prior patch [1] even if interrupts were not supported in
the SMMUv3 model.
As we are partially enabling IRQ support, we remove this option
and we make the SMMU_IRQ_CTRL always writeable

[1]: https://gem5-review.googlesource.com/c/public/gem5/+/38555

Change-Id: Ie1f9458d583a5d8bcbe450c3e88bda6b3c53cf10
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

src/dev/arm/SMMUv3.py

@@ -100,13 +100,6 @@ class SMMUv3(ClockedObject):
     reg_map = Param.AddrRange("Address range for control registers")
     system = Param.System(Parent.any, "System this device is part of")
 
-    irq_interface_enable = Param.Bool(
-        False,
-        "This flag enables software to program SMMU_IRQ_CTRL and "
-        "SMMU_IRQ_CTRLACK as if the model implemented architectural "
-        "interrupt sources",
-    )
-
     device_interfaces = VectorParam.SMMUv3DeviceInterface(
         [], "Responder interfaces"
     )

src/dev/arm/smmu_v3.cc

@@ -64,7 +64,6 @@ SMMUv3::SMMUv3(const SMMUv3Params &params) :
     tableWalkPort(name() + ".walker", *this),
     controlPort(name() + ".control", *this, params.reg_map),
     eventqInterrupt(params.eventq_irq ? params.eventq_irq->get() : nullptr),
-    irqInterfaceEnable(params.irq_interface_enable),
     tlb(params.tlb_entries, params.tlb_assoc, params.tlb_policy, this),
     configCache(params.cfg_entries, params.cfg_assoc, params.cfg_policy, this),
     ipaCache(params.ipa_entries, params.ipa_assoc, params.ipa_policy, this),
@@ -620,10 +619,9 @@ SMMUv3::writeControl(PacketPtr pkt)
             break;
         case offsetof(SMMURegs, irq_ctrl):
             assert(pkt->getSize() == sizeof(uint32_t));
-            if (irqInterfaceEnable) {
-                warn("SMMUv3::%s No support for interrupt sources", __func__);
-                regs.irq_ctrl = regs.irq_ctrlack = pkt->getLE<uint32_t>();
-            }
+            warn("SMMUv3::%s No support for GERROR and PRI interrupt sources",
+                 __func__);
+            regs.irq_ctrl = regs.irq_ctrlack = pkt->getLE<uint32_t>();
             break;
 
         case offsetof(SMMURegs, cr1):

src/dev/arm/smmu_v3.hh

@@ -103,8 +103,6 @@ class SMMUv3 : public ClockedObject
     // event queue interrupt is not supported
     ArmInterruptPin * const eventqInterrupt;
 
-    const bool irqInterfaceEnable;
-
     ARMArchTLB  tlb;
     ConfigCache configCache;
     IPACache    ipaCache;