From 5161195db5e6fab86acc721c26f68ca155c7082b Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Tue, 5 Mar 2024 13:42:16 +0000 Subject: [PATCH] dev-arm: Remove the SMMUv3 irq_interface_enable parameter The SMMU_IRQ_CTRL had been made optionally writeable by a prior patch [1] even if interrupts were not supported in the SMMUv3 model. As we are partially enabling IRQ support, we remove this option and we make the SMMU_IRQ_CTRL always writeable [1]: https://gem5-review.googlesource.com/c/public/gem5/+/38555 Change-Id: Ie1f9458d583a5d8bcbe450c3e88bda6b3c53cf10 Signed-off-by: Giacomo Travaglini --- src/dev/arm/SMMUv3.py | 7 ------- src/dev/arm/smmu_v3.cc | 8 +++----- src/dev/arm/smmu_v3.hh | 2 -- 3 files changed, 3 insertions(+), 14 deletions(-) diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py index e79fa0fcd5..ec29700814 100644 --- a/src/dev/arm/SMMUv3.py +++ b/src/dev/arm/SMMUv3.py @@ -100,13 +100,6 @@ class SMMUv3(ClockedObject): reg_map = Param.AddrRange("Address range for control registers") system = Param.System(Parent.any, "System this device is part of") - irq_interface_enable = Param.Bool( - False, - "This flag enables software to program SMMU_IRQ_CTRL and " - "SMMU_IRQ_CTRLACK as if the model implemented architectural " - "interrupt sources", - ) - device_interfaces = VectorParam.SMMUv3DeviceInterface( [], "Responder interfaces" ) diff --git a/src/dev/arm/smmu_v3.cc b/src/dev/arm/smmu_v3.cc index 00e1867eeb..4d06a8cd79 100644 --- a/src/dev/arm/smmu_v3.cc +++ b/src/dev/arm/smmu_v3.cc @@ -64,7 +64,6 @@ SMMUv3::SMMUv3(const SMMUv3Params ¶ms) : tableWalkPort(name() + ".walker", *this), controlPort(name() + ".control", *this, params.reg_map), eventqInterrupt(params.eventq_irq ? params.eventq_irq->get() : nullptr), - irqInterfaceEnable(params.irq_interface_enable), tlb(params.tlb_entries, params.tlb_assoc, params.tlb_policy, this), configCache(params.cfg_entries, params.cfg_assoc, params.cfg_policy, this), ipaCache(params.ipa_entries, params.ipa_assoc, params.ipa_policy, this), @@ -620,10 +619,9 @@ SMMUv3::writeControl(PacketPtr pkt) break; case offsetof(SMMURegs, irq_ctrl): assert(pkt->getSize() == sizeof(uint32_t)); - if (irqInterfaceEnable) { - warn("SMMUv3::%s No support for interrupt sources", __func__); - regs.irq_ctrl = regs.irq_ctrlack = pkt->getLE(); - } + warn("SMMUv3::%s No support for GERROR and PRI interrupt sources", + __func__); + regs.irq_ctrl = regs.irq_ctrlack = pkt->getLE(); break; case offsetof(SMMURegs, cr1): diff --git a/src/dev/arm/smmu_v3.hh b/src/dev/arm/smmu_v3.hh index 6a235fa385..be8525f19d 100644 --- a/src/dev/arm/smmu_v3.hh +++ b/src/dev/arm/smmu_v3.hh @@ -103,8 +103,6 @@ class SMMUv3 : public ClockedObject // event queue interrupt is not supported ArmInterruptPin * const eventqInterrupt; - const bool irqInterfaceEnable; - ARMArchTLB tlb; ConfigCache configCache; IPACache ipaCache;