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arch-arm,cpu: Replace rename modes with split reg/elem register files.

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This simplifies the O3 CPU, and removes special cases around how vector
registers are handled. Now ARM is responsible for maintaining its
different register personalities internally.

Also, this re-establishes the invariant that registers are indexed as
complete, opaque entities with no internal structure, at least as far as
the CPU is concerned.

To make sure the KVM CPU sees the correct state, we need to sync over
the vector registers if we're in 32 bit mode when moving state to or
from gem5's ThreadContext.

Change-Id: I36416d609310ae0bc50c18809f5d9e19bfbb4d37
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49147
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-09 18:02:00 -07:00
parent 25138cbb7a
commit 4fe56ff720
19 changed files with 76 additions and 374 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/arch/arm/ArmISA.py
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@@ -40,7 +40,6 @@ from m5.SimObject import SimObject
from m5.objects.ArmPMU import ArmPMU
from m5.objects.ArmSystem import SveVectorLength, ArmRelease
from m5.objects.BaseISA import BaseISA
from m5.objects.ISACommon import VecRegRenameMode
# Enum for DecoderFlavor
class DecoderFlavor(Enum): vals = ['Generic']

9
src/arch/arm/faults.cc
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@@ -494,6 +494,15 @@ ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
// be handled in AArch64 mode (to64).
update(tc);
if (from64 != to64) {
// Switching modes, sync up versions of the vector register file.
if (from64) {
syncVecRegsToElems(tc);
} else {
syncVecElemsToRegs(tc);
}
}
if (to64) {
// Invoke exception handler in AArch64 state
invoke64(tc, inst);

27
src/arch/arm/isa.cc
View File

@@ -547,24 +547,6 @@ ISA::takeOverFrom(ThreadContext *new_tc, ThreadContext *old_tc)
setupThreadContext();
}
static void
copyVecRegs(ThreadContext *src, ThreadContext *dest)
{
auto src_mode = src->getIsaPtr()->vecRegRenameMode(src);
// The way vector registers are copied (VecReg vs VecElem) is relevant
// in the O3 model only.
if (src_mode == enums::Full) {
for (auto idx = 0; idx < NumVecRegs; idx++)
dest->setVecRegFlat(idx, src->readVecRegFlat(idx));
} else {
for (auto idx = 0; idx < NumVecRegs; idx++)
for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
dest->setVecElemFlat(
idx, elem_idx, src->readVecElemFlat(idx, elem_idx));
}
}
void
ISA::copyRegsFrom(ThreadContext *src)
{
@@ -577,7 +559,14 @@ ISA::copyRegsFrom(ThreadContext *src)
for (int i = 0; i < NUM_MISCREGS; i++)
tc->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
copyVecRegs(src, tc);
for (int i = 0; i < NumVecRegs; i++)
tc->setVecRegFlat(i, src->readVecRegFlat(i));
for (int i = 0; i < NumVecRegs; i++) {
for (int e = 0; e < NumVecElemPerVecReg; e++) {
tc->setVecElemFlat(i, e, src->readVecElemFlat(i, e));
}
}
// setMiscReg "with effect" will set the misc register mapping correctly.
// e.g. updateRegMap(val)

13
src/arch/arm/isa.hh
View File

@@ -52,7 +52,6 @@
#include "arch/generic/isa.hh"
#include "debug/Checkpoint.hh"
#include "enums/DecoderFlavor.hh"
#include "enums/VecRegRenameMode.hh"
#include "sim/sim_object.hh"
namespace gem5
@@ -884,18 +883,6 @@ namespace ArmISA
return gicv3CpuInterface != nullptr;
}
enums::VecRegRenameMode
initVecRegRenameMode() const override
{
return highestELIs64 ? enums::Full : enums::Elem;
}
enums::VecRegRenameMode
vecRegRenameMode(ThreadContext *_tc) const override
{
return _tc->pcState().aarch64() ? enums::Full : enums::Elem;
}
PARAMS(ArmISA);
ISA(const Params &p);

10
src/arch/arm/isa/insts/branch64.isa
View File

@@ -248,6 +248,16 @@ let {{
CondCodesV = new_cpsr.v;
NextAArch64 = !new_cpsr.width;
// Switch between aarch64 and aarch32, or vice versa.
if (new_cpsr.width != cpsr.width) {
if (new_cpsr.width) {
// Going to aarch32.
syncVecRegsToElems(xc->tcBase());
} else {
// Going to aarch64.
syncVecElemsToRegs(xc->tcBase());
}
}
NextItState = itState(new_cpsr);
NPC = purifyTaggedAddr(newPc, xc->tcBase(),
currEL(new_cpsr), true);

4
src/arch/arm/kvm/armv8_cpu.cc
View File

@@ -256,6 +256,8 @@ ArmV8KvmCPU::updateKvmState()
for (int i = 0; i < NUM_QREGS; ++i) {
KvmFPReg reg;
if (!inAArch64(tc))
syncVecElemsToRegs(tc);
auto v = tc->readVecReg(RegId(VecRegClass, i)).as<VecElem>();
for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
reg.s[j].i = v[j];
@@ -333,6 +335,8 @@ ArmV8KvmCPU::updateThreadContext()
auto v = tc->getWritableVecReg(RegId(VecRegClass, i)).as<VecElem>();
for (int j = 0; j < FP_REGS_PER_VFP_REG; j++)
v[j] = reg.s[j].i;
if (!inAArch64(tc))
syncVecRegsToElems(tc);
}
for (const auto &ri : getSysRegMap()) {

48
src/arch/generic/ISACommon.py
View File

@@ -1,48 +0,0 @@
# Copyright (c) 2016 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject
class VecRegRenameMode(Enum):
'''Enum for Rename Mode in rename map
Elem: Each native-elem in a vector register is renamed independently.
Full: Vectors are renamed as one unit.'''
vals = ['Full', 'Elem']
__all__ = ['VecRegRenameMode']

1
src/arch/generic/SConscript
View File

@@ -45,7 +45,6 @@ SimObject('BaseInterrupts.py')
SimObject('BaseISA.py')
SimObject('BaseMMU.py')
SimObject('BaseTLB.py')
SimObject('ISACommon.py')
DebugFlag('PageTableWalker',
"Page table walker state machine debugging")

13
src/arch/generic/isa.hh
View File

@@ -43,7 +43,6 @@
#include <vector>
#include "cpu/reg_class.hh"
#include "enums/VecRegRenameMode.hh"
#include "mem/packet.hh"
#include "mem/request.hh"
#include "sim/sim_object.hh"
@@ -74,18 +73,6 @@ class BaseISA : public SimObject
virtual bool inUserMode() const = 0;
virtual void copyRegsFrom(ThreadContext *src) = 0;
virtual enums::VecRegRenameMode
initVecRegRenameMode() const
{
return enums::Full;
}
virtual enums::VecRegRenameMode
vecRegRenameMode(ThreadContext *_tc) const
{
return initVecRegRenameMode();
}
const RegClasses &regClasses() const { return _regClasses; }
// Locked memory handling functions.