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arch-arm: Fix printing of the data cache maintenance instructions

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Change-Id: I2322c7bf65b38cb07a1ea2b5dc25dfc5a0496cf0
Reviewed-by: Jack Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/7825
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Nikos Nikoleris
2017-12-20 12:13:08 +00:00
parent 760e2eb6f4
commit 4d9811cc5f
5 changed files with 14 additions and 42 deletions
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5
src/arch/arm/insts/mem64.cc
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@@ -1,5 +1,5 @@
/*
* Copyright (c) 2011-2013 ARM Limited
* Copyright (c) 2011-2013,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -53,9 +53,8 @@ SysDC64::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss, "", false);
ccprintf(ss, ", [");
ccprintf(ss, ", ");
printIntReg(ss, base);
ccprintf(ss, "]");
return ss.str();
}

12
src/arch/arm/insts/misc.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2017 ARM Limited
* Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -321,16 +321,6 @@ RegImmRegShiftOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
return ss.str();
}
std::string
MiscRegRegImmMemOp::generateDisassembly(Addr pc,
const SymbolTable *symtab) const
{
std::stringstream ss;
printMnemonic(ss);
printIntReg(ss, op1);
return ss.str();
}
std::string
UnknownOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
{

19
src/arch/arm/insts/misc.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2017 ARM Limited
* Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -344,23 +344,6 @@ class RegImmRegShiftOp : public PredOp
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class MiscRegRegImmMemOp : public PredOp
{
protected:
MiscRegIndex dest;
IntRegIndex op1;
uint64_t imm;
MiscRegRegImmMemOp(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, MiscRegIndex _dest, IntRegIndex _op1,
uint64_t _imm) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
{}
std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
};
class UnknownOp : public PredOp
{
protected:

2
src/arch/arm/isa/insts/data64.isa
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@@ -417,7 +417,7 @@ let {{
'''
msrDCZVAIop = InstObjParams("dczva", "Dczva", "SysDC64",
msrDCZVAIop = InstObjParams("dc zva", "Dczva", "SysDC64",
{ "ea_code" : msrdczva_ea_code,
"memacc_code" : ";", "use_uops" : 0,
"op_wb" : ";", "fa_code" : ";"}, ['IsStore', 'IsMemRef']);

18
src/arch/arm/isa/insts/misc.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2010-2013,2017 ARM Limited
// Copyright (c) 2010-2013,2017-2018 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1073,8 +1073,8 @@ let {{
Request::DST_POC);
EA = Op1;
'''
McrDcimvacIop = InstObjParams("mcr dcimvac", "McrDcimvac",
"MiscRegRegImmMemOp",
McrDcimvacIop = InstObjParams("mcr", "McrDcimvac",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
"postacc_code": "",
"ea_code": McrDcimvacCode,
@@ -1092,8 +1092,8 @@ let {{
Request::DST_POC);
EA = Op1;
'''
McrDccmvacIop = InstObjParams("mcr dccmvac", "McrDccmvac",
"MiscRegRegImmMemOp",
McrDccmvacIop = InstObjParams("mcr", "McrDccmvac",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
"postacc_code": "",
"ea_code": McrDccmvacCode,
@@ -1111,8 +1111,8 @@ let {{
Request::DST_POU);
EA = Op1;
'''
McrDccmvauIop = InstObjParams("mcr dccmvau", "McrDccmvau",
"MiscRegRegImmMemOp",
McrDccmvauIop = InstObjParams("mcr", "McrDccmvau",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
"postacc_code": "",
"ea_code": McrDccmvauCode,
@@ -1131,8 +1131,8 @@ let {{
Request::DST_POC);
EA = Op1;
'''
McrDccimvacIop = InstObjParams("mcr dccimvac", "McrDccimvac",
"MiscRegRegImmMemOp",
McrDccimvacIop = InstObjParams("mcr", "McrDccimvac",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
"postacc_code": "",
"ea_code": McrDccimvacCode,