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arm: Use a const ThreadContext * and readMiscRegNoEffect in places.

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Unlike readMiscReg, readMiscRegNoEffect won't have any read related
side effects and so can be used on a const ThreadContext. Also, using
a const ThreadContext * in a few functions which don't actually intend
to change state makes them usable in more situations.

Change-Id: I4fe538ba1158b25f512d3cccd779e12f6c91da6c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25944
Reviewed-by: Chun-Chen TK Hsu <chunchenhsu@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2020-02-26 04:46:11 -08:00
parent 4f4fe6f80e
commit 4d2272078f
2 changed files with 10 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/arch/arm/utility.cc
View File

@@ -397,17 +397,17 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
}
bool
isBigEndian64(ThreadContext *tc)
isBigEndian64(const ThreadContext *tc)
{
switch (currEL(tc)) {
case EL3:
return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL3)).ee;
case EL2:
return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2)).ee;
case EL1:
return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).ee;
case EL0:
return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).e0e;
default:
panic("Invalid exception level");
break;

10
src/arch/arm/utility.hh
View File

@@ -131,14 +131,14 @@ inPrivilegedMode(ThreadContext *tc)
bool inAArch64(ThreadContext *tc);
static inline OperatingMode
currOpMode(ThreadContext *tc)
currOpMode(const ThreadContext *tc)
{
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
return (OperatingMode) (uint8_t) cpsr.mode;
}
static inline ExceptionLevel
currEL(ThreadContext *tc)
currEL(const ThreadContext *tc)
{
return opModeToEL(currOpMode(tc));
}
@@ -182,7 +182,7 @@ bool ELIs64(ThreadContext *tc, ExceptionLevel el);
*/
bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
bool isBigEndian64(ThreadContext *tc);
bool isBigEndian64(const ThreadContext *tc);
/**
* badMode is checking if the execution mode provided as an argument is
@@ -368,7 +368,7 @@ int decodePhysAddrRange64(uint8_t pa_enc);
*/
uint8_t encodePhysAddrRange64(int pa_size);
inline ByteOrder byteOrder(ThreadContext *tc)
inline ByteOrder byteOrder(const ThreadContext *tc)
{
return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
};