diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index facb7f86fb..e1dffafabc 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -397,17 +397,17 @@ ELUsingAArch32K(ThreadContext *tc, ExceptionLevel el)
 }
 
 bool
-isBigEndian64(ThreadContext *tc)
+isBigEndian64(const ThreadContext *tc)
 {
     switch (currEL(tc)) {
       case EL3:
-        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL3)).ee;
+        return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL3)).ee;
       case EL2:
-        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL2)).ee;
+        return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL2)).ee;
       case EL1:
-        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).ee;
+        return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).ee;
       case EL0:
-        return ((SCTLR) tc->readMiscReg(MISCREG_SCTLR_EL1)).e0e;
+        return ((SCTLR) tc->readMiscRegNoEffect(MISCREG_SCTLR_EL1)).e0e;
       default:
         panic("Invalid exception level");
         break;
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index f16c0b5f3a..4636d1768b 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -131,14 +131,14 @@ inPrivilegedMode(ThreadContext *tc)
 bool inAArch64(ThreadContext *tc);
 
 static inline OperatingMode
-currOpMode(ThreadContext *tc)
+currOpMode(const ThreadContext *tc)
 {
-    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
+    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
     return (OperatingMode) (uint8_t) cpsr.mode;
 }
 
 static inline ExceptionLevel
-currEL(ThreadContext *tc)
+currEL(const ThreadContext *tc)
 {
     return opModeToEL(currOpMode(tc));
 }
@@ -182,7 +182,7 @@ bool ELIs64(ThreadContext *tc, ExceptionLevel el);
  */
 bool ELIsInHost(ThreadContext *tc, ExceptionLevel el);
 
-bool isBigEndian64(ThreadContext *tc);
+bool isBigEndian64(const ThreadContext *tc);
 
 /**
  * badMode is checking if the execution mode provided as an argument is
@@ -368,7 +368,7 @@ int decodePhysAddrRange64(uint8_t pa_enc);
  */
 uint8_t encodePhysAddrRange64(int pa_size);
 
-inline ByteOrder byteOrder(ThreadContext *tc)
+inline ByteOrder byteOrder(const ThreadContext *tc)
 {
     return isBigEndian64(tc) ? BigEndianByteOrder : LittleEndianByteOrder;
 };