arch-x86: Fix the "index" value for SSrcReg2.

This was set to 1, the same as SSrcReg1. That value is used to order the
registers in the source operand array. Other code then expects to find
operands in that order when, for example, looking up an index to pick
sub-parts of a register out, or to print a register name.

Since the index value of SSrcReg1 and SSrcReg2 were the same, they
wouldn't be sorted in a predictable way, meaning the code looking for
SSrcReg2's index might have found SSrcReg1's index instead and done the
wrong thing.

Change-Id: I75045e64595e249802f57d22023a7eeb7b8ac5c6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42342
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>

src/arch/x86/isa/operands.isa

@@ -90,7 +90,7 @@ def operands {{
         'SrcReg1':       foldInt('src1', 'foldOBit', 1),
         'SSrcReg1':      intReg('src1', 1),
         'SrcReg2':       foldInt('src2', 'foldOBit', 2),
-        'SSrcReg2':      intReg('src2', 1),
+        'SSrcReg2':      intReg('src2', 2),
         'Index':         foldInt('index', 'foldABit', 3),
         'Base':          foldInt('base', 'foldABit', 4),
         'DestReg':       foldInt('dest', 'foldOBit', 5),