From 4c375bd73dd3331829f73149deb4f56b8c853faf Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Mon, 1 Mar 2021 15:57:25 -0800 Subject: [PATCH] arch-x86: Fix the "index" value for SSrcReg2. This was set to 1, the same as SSrcReg1. That value is used to order the registers in the source operand array. Other code then expects to find operands in that order when, for example, looking up an index to pick sub-parts of a register out, or to print a register name. Since the index value of SSrcReg1 and SSrcReg2 were the same, they wouldn't be sorted in a predictable way, meaning the code looking for SSrcReg2's index might have found SSrcReg1's index instead and done the wrong thing. Change-Id: I75045e64595e249802f57d22023a7eeb7b8ac5c6 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42342 Maintainer: Bobby R. Bruce Tested-by: kokoro Reviewed-by: Gabe Black --- src/arch/x86/isa/operands.isa | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/isa/operands.isa b/src/arch/x86/isa/operands.isa index 504deb73fe..a1a83966e8 100644 --- a/src/arch/x86/isa/operands.isa +++ b/src/arch/x86/isa/operands.isa @@ -90,7 +90,7 @@ def operands {{ 'SrcReg1': foldInt('src1', 'foldOBit', 1), 'SSrcReg1': intReg('src1', 1), 'SrcReg2': foldInt('src2', 'foldOBit', 2), - 'SSrcReg2': intReg('src2', 1), + 'SSrcReg2': intReg('src2', 2), 'Index': foldInt('index', 'foldABit', 3), 'Base': foldInt('base', 'foldABit', 4), 'DestReg': foldInt('dest', 'foldOBit', 5),