dev-arm: Provide encapsulation by adding TranslResult::isFaulting
We don't check the fault type directly. This will improve readability once the TranslResult class will be augmented with extra fields Change-Id: I5acafaabf098d6ee79e1f0c384499cc043a75a9d Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
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@@ -184,7 +184,7 @@ SMMUTranslationProcess::main(Yield &yield)
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tr = smmuTranslation(yield);
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if (tr.fault == FAULT_NONE)
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if (!tr.isFaulting())
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ifcTLBUpdate(yield, tr);
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hazard4kRelease();
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@@ -213,7 +213,7 @@ SMMUTranslationProcess::main(Yield &yield)
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tr = smmuTranslation(yield);
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if (tr.fault == FAULT_NONE) {
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if (!tr.isFaulting()) {
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ifcTLBUpdate(yield, tr);
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issuePrefetch(next4k);
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@@ -222,14 +222,14 @@ SMMUTranslationProcess::main(Yield &yield)
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hazard4kRelease();
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}
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if (tr.fault == FAULT_NONE)
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if (!tr.isFaulting())
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microTLBUpdate(yield, tr);
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}
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hazardIdHold(yield);
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hazardIdRelease();
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if (tr.fault != FAULT_NONE)
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if (tr.isFaulting())
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panic("Translation Fault (addr=%#x, size=%#x, sid=%d, ssid=%d, "
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"isWrite=%d, isPrefetch=%d, isAtsRequest=%d)\n",
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request.addr, request.size, request.sid, request.ssid,
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@@ -297,7 +297,7 @@ SMMUTranslationProcess::smmuTranslation(Yield &yield)
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// Free PTW slot
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doSemaphoreUp(smmu.ptwSem);
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if (tr.fault == FAULT_NONE)
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if (!tr.isFaulting())
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smmuTLBUpdate(yield, tr);
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}
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@@ -414,7 +414,7 @@ void
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SMMUTranslationProcess::microTLBUpdate(Yield &yield,
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const TranslResult &tr)
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{
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assert(tr.fault == FAULT_NONE);
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assert(!tr.isFaulting());
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if (!ifc.microTLBEnable)
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return;
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@@ -446,7 +446,7 @@ void
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SMMUTranslationProcess::ifcTLBUpdate(Yield &yield,
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const TranslResult &tr)
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{
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assert(tr.fault == FAULT_NONE);
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assert(!tr.isFaulting());
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if (!ifc.mainTLBEnable)
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return;
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@@ -483,7 +483,7 @@ void
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SMMUTranslationProcess::smmuTLBUpdate(Yield &yield,
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const TranslResult &tr)
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{
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assert(tr.fault == FAULT_NONE);
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assert(!tr.isFaulting());
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if (!smmu.tlbEnable)
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return;
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@@ -788,7 +788,7 @@ SMMUTranslationProcess::walkStage1And2(Yield &yield, Addr addr,
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if (context.stage2Enable) {
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TranslResult s2tr = translateStage2(yield, walkPtr, false);
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if (s2tr.fault != FAULT_NONE)
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if (s2tr.isFaulting())
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return s2tr;
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walkPtr = s2tr.addr;
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@@ -806,7 +806,7 @@ SMMUTranslationProcess::walkStage1And2(Yield &yield, Addr addr,
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if (context.stage2Enable) {
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TranslResult s2tr = translateStage2(yield, tr.addr, true);
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if (s2tr.fault != FAULT_NONE)
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if (s2tr.isFaulting())
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return s2tr;
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tr = combineTranslations(tr, s2tr);
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@@ -924,7 +924,7 @@ SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
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Addr table_addr = context.ttb0;
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if (context.stage2Enable) {
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TranslResult s2tr = translateStage2(yield, table_addr, false);
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if (s2tr.fault != FAULT_NONE)
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if (s2tr.isFaulting())
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return s2tr;
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table_addr = s2tr.addr;
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@@ -935,7 +935,7 @@ SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
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table_addr);
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}
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if (tr.fault == FAULT_NONE)
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if (!tr.isFaulting())
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DPRINTF(SMMUv3, "Translated vaddr %#x to paddr %#x\n", addr, tr.addr);
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return tr;
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@@ -1009,7 +1009,7 @@ SMMUTranslationProcess::translateStage2(Yield &yield, Addr addr, bool final_tr)
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context.httb);
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}
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if (tr.fault == FAULT_NONE)
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if (!tr.isFaulting())
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DPRINTF(SMMUv3, " Translated %saddr %#x to paddr %#x\n",
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context.stage1Enable ? "ip" : "v", addr, tr.addr);
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@@ -1034,10 +1034,10 @@ SMMUTranslationProcess::TranslResult
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SMMUTranslationProcess::combineTranslations(const TranslResult &s1tr,
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const TranslResult &s2tr) const
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{
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if (s2tr.fault != FAULT_NONE)
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if (s2tr.isFaulting())
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return s2tr;
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assert(s1tr.fault == FAULT_NONE);
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assert(!s1tr.isFaulting());
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TranslResult tr;
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tr.fault = FAULT_NONE;
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@@ -1233,7 +1233,7 @@ void
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SMMUTranslationProcess::completeTransaction(Yield &yield,
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const TranslResult &tr)
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{
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assert(tr.fault == FAULT_NONE);
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assert(!tr.isFaulting());
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unsigned numRequestorBeats = request.isWrite ?
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(request.size + (smmu.requestPortWidth-1))
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@@ -96,6 +96,8 @@ class SMMUTranslationProcess : public SMMUProcess
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Addr addr;
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Addr addrMask;
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bool writable;
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bool isFaulting() const { return fault != FAULT_NONE; }
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};
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SMMUv3DeviceInterface &ifc;
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