From 4a4b775985d18c9e5075affb09e1ce814e88adfa Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 5 Mar 2024 17:57:45 +0000
Subject: [PATCH] dev-arm: Provide encapsulation by adding
 TranslResult::isFaulting

We don't check the fault type directly. This will improve
readability once the TranslResult class will be augmented
with extra fields

Change-Id: I5acafaabf098d6ee79e1f0c384499cc043a75a9d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
---
 src/dev/arm/smmu_v3_transl.cc | 32 ++++++++++++++++----------------
 src/dev/arm/smmu_v3_transl.hh |  2 ++
 2 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index 85554f8bd0..99ab9dbfdf 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -184,7 +184,7 @@ SMMUTranslationProcess::main(Yield &yield)
 
         tr = smmuTranslation(yield);
 
-        if (tr.fault == FAULT_NONE)
+        if (!tr.isFaulting())
             ifcTLBUpdate(yield, tr);
 
         hazard4kRelease();
@@ -213,7 +213,7 @@ SMMUTranslationProcess::main(Yield &yield)
 
                 tr = smmuTranslation(yield);
 
-                if (tr.fault == FAULT_NONE) {
+                if (!tr.isFaulting()) {
                     ifcTLBUpdate(yield, tr);
 
                     issuePrefetch(next4k);
@@ -222,14 +222,14 @@ SMMUTranslationProcess::main(Yield &yield)
                 hazard4kRelease();
             }
 
-            if (tr.fault == FAULT_NONE)
+            if (!tr.isFaulting())
                 microTLBUpdate(yield, tr);
         }
 
         hazardIdHold(yield);
         hazardIdRelease();
 
-        if (tr.fault != FAULT_NONE)
+        if (tr.isFaulting())
             panic("Translation Fault (addr=%#x, size=%#x, sid=%d, ssid=%d, "
                     "isWrite=%d, isPrefetch=%d, isAtsRequest=%d)\n",
                     request.addr, request.size, request.sid, request.ssid,
@@ -297,7 +297,7 @@ SMMUTranslationProcess::smmuTranslation(Yield &yield)
         // Free PTW slot
         doSemaphoreUp(smmu.ptwSem);
 
-        if (tr.fault == FAULT_NONE)
+        if (!tr.isFaulting())
             smmuTLBUpdate(yield, tr);
     }
 
@@ -414,7 +414,7 @@ void
 SMMUTranslationProcess::microTLBUpdate(Yield &yield,
                                        const TranslResult &tr)
 {
-    assert(tr.fault == FAULT_NONE);
+    assert(!tr.isFaulting());
 
     if (!ifc.microTLBEnable)
         return;
@@ -446,7 +446,7 @@ void
 SMMUTranslationProcess::ifcTLBUpdate(Yield &yield,
                                      const TranslResult &tr)
 {
-    assert(tr.fault == FAULT_NONE);
+    assert(!tr.isFaulting());
 
     if (!ifc.mainTLBEnable)
         return;
@@ -483,7 +483,7 @@ void
 SMMUTranslationProcess::smmuTLBUpdate(Yield &yield,
                                       const TranslResult &tr)
 {
-    assert(tr.fault == FAULT_NONE);
+    assert(!tr.isFaulting());
 
     if (!smmu.tlbEnable)
         return;
@@ -788,7 +788,7 @@ SMMUTranslationProcess::walkStage1And2(Yield &yield, Addr addr,
 
         if (context.stage2Enable) {
             TranslResult s2tr = translateStage2(yield, walkPtr, false);
-            if (s2tr.fault != FAULT_NONE)
+            if (s2tr.isFaulting())
                 return s2tr;
 
             walkPtr = s2tr.addr;
@@ -806,7 +806,7 @@ SMMUTranslationProcess::walkStage1And2(Yield &yield, Addr addr,
 
     if (context.stage2Enable) {
         TranslResult s2tr = translateStage2(yield, tr.addr, true);
-        if (s2tr.fault != FAULT_NONE)
+        if (s2tr.isFaulting())
             return s2tr;
 
         tr = combineTranslations(tr, s2tr);
@@ -924,7 +924,7 @@ SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
         Addr table_addr = context.ttb0;
         if (context.stage2Enable) {
             TranslResult s2tr = translateStage2(yield, table_addr, false);
-            if (s2tr.fault != FAULT_NONE)
+            if (s2tr.isFaulting())
                 return s2tr;
 
             table_addr = s2tr.addr;
@@ -935,7 +935,7 @@ SMMUTranslationProcess::translateStage1And2(Yield &yield, Addr addr)
                             table_addr);
     }
 
-    if (tr.fault == FAULT_NONE)
+    if (!tr.isFaulting())
         DPRINTF(SMMUv3, "Translated vaddr %#x to paddr %#x\n", addr, tr.addr);
 
     return tr;
@@ -1009,7 +1009,7 @@ SMMUTranslationProcess::translateStage2(Yield &yield, Addr addr, bool final_tr)
                         context.httb);
     }
 
-    if (tr.fault == FAULT_NONE)
+    if (!tr.isFaulting())
         DPRINTF(SMMUv3, "  Translated %saddr %#x to paddr %#x\n",
             context.stage1Enable ? "ip" : "v", addr, tr.addr);
 
@@ -1034,10 +1034,10 @@ SMMUTranslationProcess::TranslResult
 SMMUTranslationProcess::combineTranslations(const TranslResult &s1tr,
                                             const TranslResult &s2tr) const
 {
-    if (s2tr.fault != FAULT_NONE)
+    if (s2tr.isFaulting())
         return s2tr;
 
-    assert(s1tr.fault == FAULT_NONE);
+    assert(!s1tr.isFaulting());
 
     TranslResult tr;
     tr.fault    = FAULT_NONE;
@@ -1233,7 +1233,7 @@ void
 SMMUTranslationProcess::completeTransaction(Yield &yield,
                                             const TranslResult &tr)
 {
-    assert(tr.fault == FAULT_NONE);
+    assert(!tr.isFaulting());
 
     unsigned numRequestorBeats = request.isWrite ?
         (request.size + (smmu.requestPortWidth-1))
diff --git a/src/dev/arm/smmu_v3_transl.hh b/src/dev/arm/smmu_v3_transl.hh
index 156d3e6fcc..c3426b4dbb 100644
--- a/src/dev/arm/smmu_v3_transl.hh
+++ b/src/dev/arm/smmu_v3_transl.hh
@@ -96,6 +96,8 @@ class SMMUTranslationProcess : public SMMUProcess
         Addr       addr;
         Addr       addrMask;
         bool       writable;
+
+        bool isFaulting() const { return fault != FAULT_NONE; }
     };
 
     SMMUv3DeviceInterface &ifc;