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x86,cpu: Get rid of the unused IsCC StaticInst flag.

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This flag was set when some registers were used in x86, but never
actually checked by anything.

Change-Id: Id0f9847aeca5017455929ab4bbf28210288a3553
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33741
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
This commit is contained in:
Gabe Black
2020-08-30 02:48:37 -07:00
parent 5c33112fa5
commit 48f7ddc421
3 changed files with 6 additions and 8 deletions
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12
src/arch/x86/isa/operands.isa
View File

@@ -64,7 +64,7 @@ let {{
def floatReg(idx, id):
return ('FloatReg', 'df', idx, 'IsFloating', id)
def ccReg(idx, id):
return ('CCReg', 'uqw', idx, 'IsCC', id)
return ('CCReg', 'uqw', idx, None, id)
def controlReg(idx, id, ctype = 'uqw'):
return ('ControlReg', ctype, idx,
(None, None, ['IsSerializeAfter',
@@ -147,20 +147,20 @@ def operands {{
# would be retained, the write predicate checks if any of the bits
# are being written.
'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', 'IsCC',
'PredccFlagBits': ('CCReg', 'uqw', '(CCREG_ZAPS)', None,
60, None, None, '''(((ext & (PFBit | AFBit | ZFBit | SFBit
)) != (PFBit | AFBit | ZFBit | SFBit )) &&
((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0))''',
'((ext & (PFBit | AFBit | ZFBit | SFBit )) != 0)'),
'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', 'IsCC',
'PredcfofBits': ('CCReg', 'uqw', '(CCREG_CFOF)', None,
61, None, None, '''(((ext & CFBit) == 0 ||
(ext & OFBit) == 0) && ((ext & (CFBit | OFBit)) != 0))''',
'((ext & (CFBit | OFBit)) != 0)'),
'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', 'IsCC',
'PreddfBit': ('CCReg', 'uqw', '(CCREG_DF)', None,
62, None, None, '(false)', '((ext & DFBit) != 0)'),
'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', 'IsCC',
'PredecfBit': ('CCReg', 'uqw', '(CCREG_ECF)', None,
63, None, None, '(false)', '((ext & ECFBit) != 0)'),
'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', 'IsCC',
'PredezfBit': ('CCReg', 'uqw', '(CCREG_EZF)', None,
64, None, None, '(false)', '((ext & EZFBit) != 0)'),
# These register should needs to be more protected so that later

1
src/cpu/StaticInstFlags.py
View File

@@ -56,7 +56,6 @@ class StaticInstFlags(Enum):
'IsInteger', # References integer regs.
'IsFloating', # References FP regs.
'IsCC', # References CC regs.
'IsVector', # References Vector regs.
'IsVectorElem', # References Vector reg elems.

1
src/cpu/static_inst.hh
View File

@@ -170,7 +170,6 @@ class StaticInst : public RefCounted, public StaticInstFlags
bool isInteger() const { return flags[IsInteger]; }
bool isFloating() const { return flags[IsFloating]; }
bool isVector() const { return flags[IsVector]; }
bool isCC() const { return flags[IsCC]; }
bool isControl() const { return flags[IsControl]; }
bool isCall() const { return flags[IsCall]; }